NDLI: Multiple-Symbol Parallel CAVLC Decoder for H.264/AVC

Please wait, while we are loading the content...

2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

2012 IEEE Asia Pacific Conference on Circuits and Systems

2010 IEEE Asia Pacific Conference on Circuits and Systems

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

A Fully Differential 11mW 10-bit 200MS/s Sample and Hold in 0.25μ BiCMOS Technology

A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs

A CMOS Differential Difference Amplifier with Reduced Nonlinearity Error of Interpolation for Interpolating ADCs

INL Prediction Method in Pipeline ADCs

Differential OPAMP with Inherent Common-Mode Control and Self-Biased Cascodes in 120nm CMOS

Improving Source-Follower Buffer for High-Speed ADC Testing

0.7 V Monolithic CMOS LNA for 802.11 A/B WLAN Application

A New Linearity Enhancing Technique for Low Noise Amplifiers

A CMOS Current-Reused Transceiver with Stacked LNA and Mixer for WPAN

2.4 GHz High IIP3 and Low-Noise Down-conversion Mixer

Compact Modeling of MOSFETs Channel Noise for Low-Noise RF ICs Design

An 8 GHz Variable Gain Low Noise Amplifier (VGLNA) Utilizing Parallel Inter-Stage Resonance

Digital Filter Design: Global Solutions via Polynomial Optimization

Design of Arbitrary FIR Digital Filters with Group Delay Constraint

Symmetry Development for Implementing Odd-Order Lagrange-Type Variable Fractional-Delay Filters

A Methodology for Automatic Hardware Synthesis of Multiplier-less Digital Filters with Prescribed Output Accuracy

A New Method for Designing Constrained Causal Stable IIR Variable Digital Filters

New Structures for Single Filter Based Frequency-Response Masking Approach

3D Shape Acquisition and Arbitrary View Image Generation from Monocular Image Based on Primitive Decomposition

Cauchy based Rate-Distortion Optimization Model for H.264 Rate Control

A Fast Watermarking System for H.264/AVC Video

A New Efficient Approach for Removal of Impulse Noise for Color Images

A 0.18 μm CMOS Gaussian Monocycle Pulse Circuit Design for UWB

VLSI Implementation of a 600-Mbps MIMO-OFDM Wireless Communication System

RaceCheck: A Race Logic Audit Program For SoC Designs

A Development and Validation Platform for Communication SOC Design

A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications

Design of Adaptive Deblocking Filter for H.264/AVC Decoder SOC

An Adaptive Low-Power Control Scheme for On-Chip Network Applications

An Efficient Clocking Scheme for On-Chip Communications

Semi-Blind Time Domain Equalization for MIMO-OFDM Systems

Linear Precoding For MIMO STC-OFDM And Blind Channel Estimation

Multi-degree Random Cyclic Delay Diversity in MISO Systems with Frequency-Domain Scheduling

Throughput Maximization in Multiuser MIMO Downlink with Individual QoS Constraints

Iterative Symbol-by-symbol Decision Feedback Detection for MIMO-ISI Channels

An EM-Based Joint Channel Estimation and Data Detection for SIMO Systems

Development of a Wireless Sensor Network System for Power Constrained Applications

Design of a Long-Range Wireless Sensor Node

Hierarchical Decision-making of Multi-sensor System for State Estimation of Machining Process

An Optimized Scheme of Energy Consumption in Wireless Sensor MAC Protocol

A Novel Smart Temperature Sensor: Extracting Run-time Temperature within SRAM Cells

Noise Analysis and Simulation of Chopper Amplifier

A Low-power 7-b 33-Msamples/s Switched-current Pipelined ADC for Motor Control

Low Power Current-Mode Algorithmic ADC in Half Flash (BCD)

A Switched-Voltage High-Accuracy Sample/Hold Circuit

A 1-V 2.5-mW Transient-Improved Current-Steering DAC using Charge-Removal-Replacement Technique

Continuous Time Delta-Sigma Modulators with Arbitrary DAC Waveforms

A New Approach for DAC Non-linearity Compensation in Continuous Time Delta Sigma Modulators

Sub-1 V Current Mode CMOS Integrated Receiver Front-end for GPS System

High Power CMOS Power Amplifier for WCDMA

A Fast 1.9 GHz Fractional-N/Integer Frequency Synthesizer with a Self-tuning Algorithm

A CMOS Digitally Controlled RF Variable Gain Amplifier

A 3.125-GHz Limiting Amplifier for Optical Receiver System

A 2.4-GHz/5-GHz Low Power Pulse Swallow Counter in 0.18-μm CMOS Technology

Filterbank Framework for Multicarrier Systems with Improved Subcarrier Separation

Performance Analysis of the Deficient Length EDS Adaptive Algorithm

An Alternate Approach for Developing Higher Radix FFT Algorithms

Signature Verification using Velocity-based Directional Filter Bank

Multidimensional Parameters Estimation of Array Signal Based on Steering Vector

Wavelet Packet Transform for Scalable Audio Encoder

Design of a Low Power Architecture for CABAC Encoder in H.264

Frame Based Error Concealment in H.264/AVC by Refined Motion Prediction

Matched Block Detection and Motion Vector Salvage Methods for Fast H.264/AVC Inter Mode Decision

An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders

Combined CAVLC Decoder and Inverse Quantizer for Efficient H.264/AVC Decoding

Modified MMSE DMC and Edge Reserving Concealment for Improving H.264 Error Resilience

An All-MOS High Linearity Voltage-to-Frequency Converter Chip with 520 KHz/V Sensitivity

An ASIC Implementation of Lifting-Based 2-D Discrete Wavelet Transform

VLSI Realization of Adaptive Equalizers of SIMO FIR Second Order Volterra Channels

Design and Implementation of a Schedulable DMAC on an AMBA-Based SOPC Platform

Implementation of the Gamma (γ) Line System Similar to Non-linear Gamma Curve with 2bit Error(LSB)

Adiabatic Smart Card

Space-Time Decision-Directed Equalizer for SIMO Systems based on Affine Projection Algorithm

A Turbo-BLAST method with Non-Linear MMSE Detector for MIMO-OFDM systems

An Effective SLM-PRSC Hybrid Scheme for OFDM PAPR Reduction Based on Repeated Utilization of Identical PRSC Sequences in Time Domain

Efficient Buffer Management for Retry Mechanism in InfiniBand

Enhanced Degree Computationless Modified Euclid's Algorithm

A VLSI Design of High Speed Bit-level Viterbi Decoder

Global Convergence Analysis of Delayed Bidirectional Associative Memory Neural Networks

Using ANN To Predict The Best HUB Location

A Generic Architecture for Intelligent System Hardware

Recognition of Musical Instruments

Pareto based Multi-objective Mapping IP Cores onto NoC Architectures

Minimal Set of Essential Resource Disjoint Pairs for Exploring Feasible 3D Schedules

A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication Systems

A 4-bit 1.356 Gsps ADC Using Current Processing Method

A 6-bit 2.704Gsps DAC for DS-CDMA UWB

A 14b 100MS/s 3.4mm2 145mW 0.18um CMOS Pipeline A/D Converter

An I/Q channel 12 bit 120MS/s CMOS DAC with three stage thermometer decoders for WLAN

A 0.18μm CMOS Fully Differential RF Demodulator for FM-UWB Based P-PAN Receivers

A 0.18-μm CMOS UWB Low Noise Amplifier for Full-Band (3.1-10.6GHz) Application

3~5 GHz Cascoded UWB Power Amplifier

A Fully Integrated 3 to 5 GHz CMOS Mixer with Active Balun for UWB Receiver

A Novel FFT Processor for OFDM UWB Systems

Design of Optimal Decimation and Interpolation Filters for Low Bit-Rate Image Coding

Multiple Description Image Coding With Hybrid Redundancy

Image Enhancement Algorithm for Hexagonal Cellular Neural Networks

Minimization of L2-Sensitivity for 2-D Separable-Denominator State-Space Digital Filters Subject to L2-Scaling Constraints

Design of Delta Operator Based 2-D IIR Filters Using Symmetrical Decomposition

A Low Complexity High Quality Interger Motion Estimation Architecture Design for H.264/AVC

Unequal-arm Adaptive Rood Pattern Search with Early Terminations For Fast Block-matching Motion Estimation on H.264

Motion Vector Estimation and Adatptive Refinement for the MPEG-4 to H.264/AVC Video Transcoder

Exploiting Reference Frame History in H.264/AVC Motion Estimation

Fast Motion Estimation Algorithm by Finite-State Side Match for H.264 Video Coding Standard

Transistor Realization of Reversible TSG Gate and Reversible Adder Architectures

Redundant Adders Consume Less Energy

A CAM/WTA-Based High Speed and Low Power Longest Prefix Matching Circuit Design

Design of Clocked Transmission Gate Adiabatic Logic Circuit Based on the 3ECEAC

A New Class AB Current-Mode Circuit for Low-Voltage Applications

A General Formulation of Analog-to-Digital Converters Using Parallel Sigma-Delta Modulators and Modulation Sequences

A Resolution- and Rate- Scalable Image Subband Coding Scheme with Backward Coding of Wavelet Trees

Design of Time Domain Equalizers Incorporating Radio Frequency Interference Suppression

Flexible Filter Bank Dimensioning for Multicarrier Modulation and Frequency Domain Equalization

Prototype Filter Design for a Cosine-Modulated Filterbank Transmultiplexer

VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWT

Merged-Cascaded Systolic Array for VLSI Implementation of Discrete Wavelet Transform

DCT Sign Only Correlation and Its Application to Image Registration

Image Registration using Fractional Fourier Transform

Design of an Area Efficient High-Speed Color FDWT Processor

System Design of Implantable Micro-stimulator for Medical Treatments

A Wide-Range and High PSRR CMOS Voltage Reference for Implantable Device

Some Recent Developments in the Design of Biopotential Amplifiers for ENG Recording Systems

A Micropower CMOS Amplifier for Portable Surface EMG Recording

Low Power SAW-Based Oscillator for an Implantable Multisensor Microsystem

A Miniaturized, Power-Efficent Stimulator Output Stage Based on the Bridge Rectifier Circuit

A Low-Power Low-Voltage Amplifier for Heart Rate Sensor

Design of 3-4GHz Tunable Low Noise LC-QVCO for IEEE 802.11a WLAN Application

A 6.5-GHz LC VCO with Integrated-Transformer Tuning

A CMOS Dual-Band Voltage Controlled Oscillator

A Low-Voltage 2.4GHz VCO with 3D Helical Inductors

0.8 V GPS band CMOS VCO with 29% Tuning Range

A Novel 16-bit CMOS Digitally Controlled Oscillator

A Wide Input-Range ΣΔ Modulator for Applications to Spread-Spectrum Clock Generator

Bit-Serial Digital Filter Implementation using a Custom C Compiler

Towards an Efficient Simulation of Multi-Language Descriptions of Heterogeneous Systems

FPGA Prototyping of Spatio-temporal 2D IIR Broadband Beam Plane-wave Filters

Broadband Beamforming of Bandpass Plane Waves using 2D FIR Trapezoidal Filters at Baseband

Efficient Implementation of the Fast Filter Bank For Critically Decimated Systems

Optimized Design of Extrapolated Impulse Response FIR Filters with Raised-Cosine Windows

A High-Performance VLSI Architecture for Intra Prediction and Mode Decision in H.264/AVC Video Encoding

Memory Access Optimization of Motion Estimation Algorithms on a Native SIMD PLX Processor

Implementation of a H.264 decoder with Template-based Communication Refinement

Complexity Based Fast Coding Mode Decision for MPEG-2 / H.264 Video Transcoding

Low Complexity High Quality Fractional Motion Estimation Algorithm and Architecture Design for H.264/AVC

An Improved Soft-Input CAVLC Decoder for Mobile Communication Applications

High Performance Context Adaptive Variable Length Coding Encoder for MPEG-4 AVC/H.264 Video Coding

Asynchronous Design Methodology for an Efficient Implementation of Low power ALU

Low Power Multiplier Designs Based on Improved Column Bypassing Schemes

A High-Speed Baugh-Wooley Multiplier Design Using Skew-Tolerant Domino Techniques

Low Power Multiplier with Bypassing and Tree Strucuture

Asynchronous Design of Modular Multiplication Using Adaptive Radix Computation

New Bit-Parallel Systolic Multiplier over GF(2m) Using The Modified Booth's Algorithm

High-Performance Low-Power Full-Swing Full Adder Cores with Output Driving Capability

Advances in Global Optimization: Novel Function Transformation Approaches

A Filled Function Method for Box-constrained System of Nonlinear Equations

An Optimization Problem on Two-Partition of Jobs for Profit Allocation

A Recursive Digital Filter Design using Global Optimization Technique

Linear Incentive Contract for Principal-agent Problem with Asymmetric Information and Moral Hazard

Results on Exactness Properties of the HP-ALF for Inequality Constraints

A Total Unimodularity Based Branch-and-Bound Method for Integer Programming

Hybrid Dual-Operating-Mode PWM Based Sliding Mode Controllers for DC-DC Converters

Practical Implementation of Sliding Mode Control for Boost Converter

Current-Mode Converters with Adjustable-Slope Compensating Ramp

Steady-State Performance Analysis of Cascade Boost Converters

A Monolithic Boost Converter with an Adaptable Current-Limited PFM Scheme

On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology

Embedded DC-DC Voltage Down Converter for Low-Power VLSI Chip

Design of a Wireless Power Supply Receiver for Biomedical Applications

A Novel DPWM Based on Fully Table Look-Up for High-Frequency Power Conversion

An Implantable SOC Chip for Micro-stimulating and Neural Signal Recording

A Novel Current Feed-back Sub-Nano-Siemen Transconductance Circuit Suitable for Large Time-Constant Bio-medical Applications

Design of Low-Frequency Low-Pass Filters for Biomedical Applications

A 140-dB CMRR Low-noise Instrumentation Amplifier for Neural Signal Sensing

Parallel Discovery of Transcription Factor Binding Sites

Low Power Bootstrapped CMOS Differential Cross Coupled Driver

A Wide Dynamic Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback

Two Novel Phase-Frequency Detectors

Detailed Behavioral Modeling of Bang-Bang Phase Detectors

Fourier Series Analysis for Nonlinearities Due to the Power Supply Noise in Open-Loop Class D Amplifiers

An Analysis of THD in Class D Amplifiers

A BiCMOS Low Voltage Low Distortion Class AB Amplifier

A Genetic Algorithm Employing Correlative Roulette Selection for Optimization of FRM Digital Filters over CSD Multiplier Coefficient Space

Frequency-Response Masking Approach for Design of Intermediate Frequency Filters in CDMA and Wideband GSM Modules

On the Use of Lyapunov Functions for the Design of Complex FIR Digital Filters

An Algorithm for the Design of Multiplierless IIR Filters as a Parallel Connection of Two All-Pass Filters

Mitigation of Narrowband Interference in SC Transmission with Filter Bank Equalization

Theory, Lattice Structure and Design of Unequal Length Linear Phase Perfect Reconstruction Filter Banks with More Flexible Length Profile

Design of High-speed, Low-power FIR Filters with Fine-grained Cost Metrics

A CABAC Encoding Core with Dynamic Pipeline for H.264/AVC Main Profile

Predictive Mode Searching Policy for H.264/AVC Intra Prediction

Fast Picture and Macroblock Level Adaptive Frame/Field Coding for H.264

A Fast Macroblock Mode Decision Algorithm for H.264

Cost-Effective Hardware Sharing Architectures of Fast 8×8 and 4×4 Integer Transforms for H.264/AVC

New Encoding of 8×8 DCT to make H.264 Lossless

A Convex Optimization-Based Object-Level Rate Control Algorithm for MPEG-4 Video Object Coding

A Certain SA Solver TOSA for Global Placement

A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints

Design Partitioning for Reducing Crosstalk Analysis Time

Replacement of Register with Delay Element for Reducing the Area of Pipelined Circuits

Area Recovery by Abutted Cell Placement: Can Fillers be Killers? An Eye-opening Viewpoint!

Post-placement Thermal Via Planning for 3D Integrated Circuit

Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction

Uniform DFT Filter Bank with Finite Precision Prototype Filters

Fourth-Order Discrete-Time Variable Centre Frequency Bandpass Sigma-Delta Modulator

Post-Filtering Techniques For Directive Non-Stationary Source Combined With Stationary Noise Utilizing Spatial Spectral Processing

Blind Subband Beamforming for Speech Enhancement of Multiple Speakers

An Optimisation Approach to Robust Estimation of Multicomponent Polynomial Phase Signals in Non-Gaussian Noise

Exploiting Concurrency in System-on-Chip Verification

Bistatic Ambiguity Function and DOA Estimation for PCL Radar

Single DC/AC CCFL Inverter for Large Size LCD TV with Burst Control

Fuzzy-based Active and Reactive Control for Brushless Doubly-fed Wind Power Generation System

Effects of PV Grid-Connected System Location on a Distribution System

The Calculation of the Voltage Distribution in Transformer Windings under VFTO Based on FDTD Method

A High Frequency Circuit Model for Current Transformer Based on the Scattering Parameter

High Level Synthesis with Multiple supply Voltages for Energy and Combined Peak Power Minimization

Peak Power Minimization through Power Management Scheduling

Development of a CMOS Imaging Device for Functional Imaging Inside the Mouse Brain

Stability and Compensation Technique for a CMOS Amperometric Potentiostat Circuit for Redox Sensors

A Linear LDO Regulator with Modified NMCF Frequency Compensation Independent of Off-chip Capacitor and ESR

Endothelial Cell Image Enhancement using Decimation-Free Directional Filter Banks

Testing the Quality of Magnetic Gradient Fields for Studying Self-Diffusion Processes in Biological Specimens by Magnetic Resonance Methods

Current-mode Universal Filter with Four Inputs and One Output using CDTAs

Current-mode Active-only Universal Filter

Independent Tunable-Q Current-mode OTA-C Universal Filter

Oscillation-based Test Method for Continuous-time OTA-C Filters

Synthesis of Delay Equalized Time-Varying Butterworth Filters

Multirate Filters: An Overview

Stepped Triangular CIC Filter for Rational Sample Rate Conversion

A Novel Systematic Approach for Synthesizing Multiplication-Free Highly-Selective FIR Half-Band Decimators and Interpolators

Implementation of Polyphase Decomposed FIR Filters for Interpolation and Decimation Using Multiple Constant Multiplication Techniques

On the Design of Cosine-Modulated Filter Banks Using Recurrent Frequency-Response Masking

The Dyadic Curvelet Transform for Multiscale Topological Complex Networks

Subword Parallel Architecture for Connected Component Labeling and Morphological Operations

Markov Chain Monte Carlo Super-resolution Image Reconstruction With Artifacts Suppression

An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture

A One-Dimensional Technique for Embedding Data in A JPEG Color Image

Techniques of Power-gating to Kill Sub-Threshold Leakage

Accurate and Fast Estimation of Junction Band-to-Band Leakage in Nanometer-Scale MOSFET

Leakage Optimized DECAP Design for FPGAs

Fine-grain Sleep Transistor Placement Considering Leakage Feedback Gate

A New Thermal-Conscious System-Level Methodology for Energy-Efficient Processor Voltage Selection

Jointly Optimized Modulated-Transmitter and Receiver FIR MIMO Filters

Comparison of Filter Bank Based Multicarrier Systems with OFDM

Nonlinear and Decision-Oriented Signal Processing for OFDM-Based Wireless Communications

A Real-Time Digital Baseband Channel Emulation System for OFDM Communications

Synchronization Issues in OFDM Systems

Footstep Recognition with Psyco-acoustics Parameter

A Robust Anti-collusion Coding in Digital Fingerprinting System

Automatic Detection and Segmentation of Text in Low Quality Thai Sign Images

Real-Time Implementation of a Particle Filter with Integrated Voice Activity Detector for Acoustic Speaker Tracking

Early Detection on the Condition of Pancreas Organ as the Cause of Diabetes Mellitus by Real Time Iris Image Processing

On Finding a Solution in the Core of a Multicommodity Flow Game on a Spider

Sequence-Pair Based Compaction under Equi-Length Constraint

Realizability of Score Sequence Pair of an (r1l, r12, r22)-Tournament

Kernel Extraction for Watermarking Combinational Logic Networks

Wavelet Packet Decomposition-Based Fuzzy Clustering Algorithm for Gene Expression Data

An Active-RC Complex Filter with Mixed Signal Tuning System for Low-IF Receiver

Generalized Bandpass Sampling with Complex FIR Filtering

A 0.18μm CMOS Receiver with Decision-feedback Equalization for Backplane Applications

The Analysis of Phase-jitter Variance in the Third-order CPPLL Frequency Synthesizer

An Efficient Realization of the Decision Feedback Equalizer using Block Floating Point Arithmetic

Frequency Transformations of IIR Filters with Filter Bank Applications

Adjustable Fractional-Delay FIR Filters Using the Farrow Structure and Multirate Techniques

Parallelisation of Digital Signal Processing in Uniform and Reconfigurable Filter Banks for Satellite Communications

Design of Real and Complex Linear-Phase IIR Modified QMF Banks

A Determination Method for Initial Values of Coplanar Camera Calibration Parameters

Implementation of an AMBA-Compliant IP for H.264 Transform and Quantization

VSIP : Implementation of Video Specific Instruction-set Processor

An Implementation of H.264 Intra Predictor Based on Sub-sampling

SoC Design of Speaker Connection System by Efficient Cosimulation

On the Configurable Multiprocessor SoC Platform with Crossbar Switch

DFM-aware Routing for Yield Enhancement

A Spectral Stochastic Collocation Method for Capacitance Extraction of Interconnects with Process Variations

Three DFM Challenges: Random Defects, Thickness Variation, and Printability Variation

A Hitchhiker's Guide to the DFM Universe

Prospects and Challenges of Handling Power Bus Modeling and Supply Noise in Package-Chip C0-design Approach

A Low-power 4-T SAM Design for OFDM Demodulators in DVB Receiversers

Pipelined Parallel Architectures for High Throughput Turbo Decoding

Linear Adaptive Blind Equalizers of Non Linear SIMO FIR Channels

Design of a Dynamic PCM Selector for Non-deterministic Environment

FPGA-Based Design of a Pulsed-OFDM System

Edge Detection on the Bayer Pattern

License Plate Localization of Moving Vehicles in Complex Scene

Study of Real-Time Detecting System for Driver's Safety

Feature Point Tracking for Car Speed Measurement

Video Vehicle Detection Algorithm based on Virtual-Line Group

New Reconfiguration Algorithm for Degradable VLSI Arrays

Automatic Identification of Custom Functions for Embedded Processors with MIMO Extensions

A Clustering ILP Model for Fast Instruction Selection in Embedded Applicated Specific Processor Design

Optically Reconfigurable Gate Arrays vs. ASICs

A Reconfigurable Multi-Modulus Modulo Multiplier

A Reconfigurable Satlin/Sigmoid/Gaussian/Triangular Basis Functions Computation Circuit

Matrix Inversion on Reconfigurable Hardware using Binary-coded z-path CORDIC

A New Choice of Influence Function for Robust Multiuser Detection in Non-Gaussian Channels

A Combined Residual Frequency and Sampling Clock Offset Estimation for OFDM Systems

MPOE Based Prefiltering and MRT Beamforming for DS-CDMA Systems

Interference Suppression in DS-SS Systems with Modified Discrete Fourier Transform

Even-order Distortion Rejection Technique for Self-homodyne OFDM Systems

Hardware Architecture of Improved Tomlinson-Harashima Precoding for Downlink MC-CDMA

Maximum Likelihood Timing and Carrier Frequency Offset Estimation for OFDM systems with Periodic Preambles

Inverse Tangent Based Adaptive IIR Notch Filter

Multi-Standard Delta-Sigma Decimation Filter Design

A Closed Form Solution to L2-Sensitivity Minimization of Second-Order Digital Filters Subject to L2-Scaling Constraints

Gramian-Preserving Frequency Transformation for State-Space Digital Filters

Fully-multiplexed First-order 3D IIR Frequency-Planar Filter Module

On the Properties And Design of Stable IIR Transfer Functions Generated Using Fibonnaci Numbers

Multirate Filter Bank-based Conversion of Image Resolution

Enhanced Partial Distortion Sorting Fast Motion Estimation Algorithm for Low-Power Applications

Multiple-Symbol Parallel CAVLC Decoder for H.264/AVC

A Memory Bandwidth Optimized Interpolator for Motion Compensation in the H.264 Video Decoding

A Fast Algorithm and Its Architecture for Motion Estimation in MPEG-4 AVC/H.264 Video Coding

Priority-Based Normalized Partial Distortion Search Algorithm for Fast Motion Estimation

A Subsample-based Motion Estimation for Quality-Stationary Video Coding

A High Throughput and Data Reuse Architecture for H.264/AVC Deblocking Filter

GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design

The Multiple Point Global Lanczos Method for MIMO Interconnect Model-Order Reductions

Low-Power Bus Transform Coding for Multilevel Signals

Width and Timing-Constrained Wire Sizing for Critical Area Minimization

Optimizing Interconnect for Performance in Standard Cell Library

Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion

Optimal Network Analysis in Hierarchical Power Quad-Grids

A Low-Power Technique Based on Charge Injection and Current-Saving Methods for Match-Line Sensing in Content-Addressable Memories

Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline

Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory

Multiple-valued SRAM with FG-MOSFETs

Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search

An Automatic Cache Generator Based on Content-Addressable Memory

Memory-Efficient Accelerating Schedule for LDPC Decoder

WLAN Location Determination Systems

Design of AND and NAND Logic Gate Using NDR-BASED Circuit Suitable for CMOS Process

On an Efficient Closed Form Expression to Estimate the Crosstalk Noise in the Circuit with Multiple Wires

Applications of the Superposition Theorem to Nonlinear Resistive Circuits

New Criteria Enhancing Robustness and Efficiency of Solving Systems of Circuit Equations

Phase Hits Insensitive CSRO

Design of Interconnected Bus for Low Power Based on Boolean Process

Power Analysis for the MOS AC/DC Rectifier of Passive RFID Transponders

Reliability Improvement of a Distribution System Using PV Grid Connected System with Tie Switch

FACTS Devices Applications on Power System to Improve the Angle Stability

Generalized Steady-State Analysis on Developed Series of Cascade Boost Converters

Implementation of a Symbolic Circuit Simulator for Topological Network Analysis

Controllability Gramian for Optimal Placement of Power System Stabilizers in Power Systems

Load Share Controller IC and Its Control Strategy Design

Novel High Speed and Low Power Single and Double Edge-Triggered Flip-Flops

New Methods for QDDFS with Millions' Compression Ratio

The Inverse Matrix for the Conversion Between Standard and Normal Bases

Optimum Supply and Threshold Voltages and Transistor Sizing Effects on Low Power SOI Circuit Design

Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs

A Novel Low Power NOR gate in SOI CMOS Technology

Circuit Area-latency Optimization Technique for High-precision Elementary Functions

High-Level Synthesis for Self-Timed Systems

Generation of Fixed Polarity Arithmetic Spectra for Ternary Functions

Efficient Implementation of AES IP

Impacts of Inductance on the Figures of Merit to Optimize Global Interconnect

Optical Interconnect Technology; Photons Based Signal Communication

Low Power Combinational Multipliers using Data-driven Signal Gating

Synthesis of Finite State Machines for Low Power and Testability

An Efficient Self-Transposing Memory Structure for 32-bit Video Processors

Highly Linear and Efficient AlGaAs/GaAs HBT Power Amplifier with Integrated Linearizer

A Fast Bit-Interleaving RSA Cryptosystem Based on Radix-4 Cellular-Array Modular Multiplier

A 1V 2.4GHz Down Conversion Folded Mixer

Analysis and Design of High Performance, Low Power Multiple Ports Register Files

Modeling a Digital Hearing Instrument for Developing and Evaluating Adaptive Feedback Cancellation Algorithms

On-Chip Supply Voltage Measurement Technique

A Compact Equivalent Circuit Model of HVLDMOS and Application in HIVC Design

The Setup of Artifical Neural Network Model for Estimating the Insulator Pollution Degree

Low-Power Exponential V-I Converter Using Composite PMOS Transistors

Five-State Logic Using MOS-HBT-NDR Circuit by Standard SiGe BiCMOS Process

Simplification of Exclusive-or Sum-of-Products Expressions Through Function Transformation

2PADCL: Two Phase drive Adiabatic Dynamic CMOS Logic

Stacked Active Loads For Low Power, High Speed GaAs Digital Circuits (SALFL)

Low Complexity Architecture for Multiplicative Inversion in GF(2m)

An Area-Efficient Design for Modular Inversion in GF(2m)

Physics-based Modeling and Simulation of Dual Material Gate(DMG) LDMOS

Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic

Analysis and Measurement of Cross Modulation Distortion in WCDMA Receivers

A High-Speed Low-Complexity VLSI SISO Architecture

Frequency Synthesizer for Wireless Applications using TDTL

Adaptive ZCDPLL for Quadrature-Quadrature PSK Carrier Recovery

Digital GFSK Carrier Synchronization

A Novel Neural Network GA-Optimized Controller for QoS Support in Wireless MACs

Performance Analysis of Successive Interference Cancellation in Multiuser CDMA over Flat Channels

Reduced-Complexity Concurrent Systolic Implementation of the Discrete Sine Transform

Area/Delay Efficient Recoding Methods for Parallel CORDIC Rotations

Ultra Low Power Weak Inversion Current Steered Digital to Analog Converter

Low Power FIR Filter Realization using Minimal Difference Coefficients: Part I - Complexity Analysis

Low Power FIR Filter Realization Using Minimal Difference Coefficients: Part II - Algorithm

A Comparison of Pipelined RAG-n and DA FPGA-based Multiplierless Filters

A Fully Pipelined Multiplierless Architecture for 2D Convolution with Quadrant Symmetric Kernels

Constructing Better Partial Sums Based on Energy-Maximum Criterion for Fast Encoding of VQ

A Self-Grouping and Table-Merging Algorithm for VLC-Based Video Decoding System

A Quick Scene Search with Constructed Mapped Charts for TV Sport Programs

Accelearation of Full-Search Algorithm on SIMD Architectures by Using Eight-Bit Partial Sums of Four Luminance Values

A Fast Hexagon-Based Search Algorithm on SIMD Architectures

Robust Scalable Video Transmission using Object-Oriented Unequal Loss Protection over Internet

The VLSI Design of Motion Adaptive De-interlacing with Horizontal and Vertical Motions Detection

A Novel Input Stage Based on DTMOS for Low-Voltage Low-Noise Operational Amplifier

A Frequency Compensation Technique for Variable Output Low Dropout Regulators

Design and Analysis of a VHF OTA-C Cell for Optimum Phase Response

Separation of Individual Noise Sources from Compound Noise Measurements in Digital Circuits

Model-Order Reduction Algorithm with Structure Preserving Techniques

Low-Power Crosstalk Avoidance Encoding for On-Chip Data Buses

Sensitivity Analysis of Uniform and Nonuniform Transmission Lines

Operation Scheduling for False Loop Free Circuits

Fixed Polarity Arithmetic Expansions Calculation from Disjoint Cubes Representation of Ternary Functions

Disjoint Cubes Generation Algorithm for Multiple-Valued Functions

Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits

Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials

A Method for the Correction of N-Ports Scattering Parameters Measurement

Fast Conversion for Large Canonical OR-Coincidence Functions

A Simple Synthesis Technique of PWM Signal

Real-Time Image Stabilization for Digital Video Cameras

Unified Signed-Digit Number Adder for RSA and ECC Public-key Cryptosystems

An Efficient Algorithm for DPA-resistent RSA

A 1.6GHz Downconverter Mixer in 0.25μm CMOS

Translinear Loop Principle and Identification of the Translinear Loops

A 12-bit CMOS Current Steering D/A Converter for Embedded Systems

An FPGA Implementation of Array LDPC Decoder

A 2.4-GHz CMOS Tunable Image-Rejection Low-Noise Amplifier with Active Inductor

A Real-time Boat Surveillance System Using GPRS

Non-Data Aided SBIB Receiver

Single Amplifier Sigma Delta Modulator With Input Feedforward

A Tunable Ultra-Wideband Pulse Generator Using a Variable Edge-Rate Signal

Design and VLSI Architecture of a Channel Equalizer Based on Adaptive Modulation for IEEE 802.11a WLAN

The Design of Anti-collision Mechanism of UHF RFID System based on CDMA

On The Realization of Active MURC Filter wth a Single Pole Amplifier

Error Concealment Using Digital Watermarking

An Iterative Super-Resolution Reconstruction of Image Sequences using Fast Affine Block-Based Registration with BTV Regularization

Power Consumption in Handheld Computers

From Software to Hardware - A Novel TLM Auto-Generating Method

Improved Robust Multiuser Detection in Non-Gaussian Channels Using a New M-Estimator and Spatiotemporal Chaotic Spreading Sequences

Generation of Panoramic Image from Aerial Video utilizing JP2K Wavelet for River Surveillance

A Harmonic Reduction Scheme in SPWM

Water Level Detection for River Surveillance utilizing JP2K Wavelet Transform

Dual Mode Architecture for Deblocking Filtering in H.264/AVC Video Coding

Efficient Hardware Implementation for H.264/AVC Motion Estimation

Design and Implementation of a 2-level FSK Digital Modems Using CORDIC Algorithm

Power Management in Circuits Design

A Novel Structure of Conjunction Decision Feedback Equalizer for Nonlinear Channels

A Novel Method for Systematic Error Prediction of CMOS Folding and Interpolating ADC

Low Voltage Analogue Multiplier

A Low-power Tunable Bandpass Amplifier for RF Applications

Low Voltage High-Performance Class-AB FGMOS Buffer

Electrocardiogram Analysis with Adaptive Feature Selection and Support Vector Machines

Optimizing High Speed Flip-Flop Using Genetic Algorithm

Engery-Efficient Double-Edge Triggered Flip-Flop Design

A 0.9V 10GHz 71μW Static D Flip-flop by using FinFET Devices

Another Look at the Sequential Multiplier over Normal Bases

A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment

Level Selection Based 4-PAM Transmitter for Chip to Chip Communication

Research of Phase-Inversion Symmetric Modulation Based on DSB Communication System

Digital Audio Broadcasting System Modeling and Hardware Implementation

Rapid Acquisition of Ultra-Wideband Signals in Multipath Environments

Digital Network Echo Cancellation Using Genetic Algorithm and Combined GA-LMS Method

Chua Circuit Based Reconfigurable Computing System

Unscented Kalman Filter and Particle Filter for Chaotic Synchronization

Exploiting Chaos for Computation

Reconfigurable Logic Element using a Chaotic Circuit

Exploiting Nonlinear Dynamics to Search for the Existence of Matches in a Database

Codeblock-Based Concealment Scheme for JPEG2000 Images in Lossy Packet Networks

Progressive Technique for Rate Distortion Optimization in JPEG2000

4K SHD Real-Time Video Streaming System With JPEG 2000 Parallel Codec

Application of Multi-ported CAM for Parallel Coding

A Novel Hybrid Approach of Color Image Segmentation

On the Number of 3-D IC Floorplan Configurations and a Solution Perturbation Method with Good Convergence

Thermal Driven Module Placement Using Sequence-pair

Efficient Algorithms for Hardware/Software Partitioning to Minimize Hardware Area

Global Interconnect Analysis and Optimization for Nanometer Scale VLSI

A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI Circuits

Reducing Noisy-Coefficient Problem in Non-Continuous Adaptive Feedback Canceller for Hearing Aids

A Robust Correlation Method for Solving Permutation Problem in Frequency Domain Blind Source Separation of Speech Signals

Blind Determination of the Signal to Noise Ratio of Speech Signals Based on Estimation Combination of Multiple Features

Design of IP Media Server for Voice Conference Application

Implementation of MPEG-2 AAC on 16-bit Fixed-Point DSP

DWDM Demultiplexer Using Compound Optical Ring Resonator with Fiber Bragg Grating

Optical Front-Ends for Low-Cost Laser-Based 10-Mbps Free-Space Optical Transceiver

A Standalone Printing USB Host Device Prototype

Narrow-Band FM Multi-Tone FSK Modem: TMS320C6000 Based Testbed Implementation and Performance Analysis

Genetic Algorithm based Approximants for Discrete Time Systems: A Computer-Aided Approach

A 2-D Systolic Array for High-Throughput Computation of 2-D Discrete Fourier Transform

A Low-Power Reconfigurable Mixed-Radix FFT/IFFT Processor

A Low Multiplier and Multiplication Costs 256-point FFT Implementation with Simplified Radix-24 SDF Architecture

A Grouped Fast Fourier Transform Algorithm Design For Selective Transformed Outputs

A Discrete STFT Processor for Real-time Spectrum Analysis

A Low Cost/Low Power Chaos-based Transceiver Exploiting Ergodicity

Look-up Table Based Chaotic Encryption of Audio Files

Design of A Low Power High Entropy Chaos-Based Truly Random Number Generator

A Current-Sampling-Mode Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach Driven by Quantized Nonlinear Waveforms

Chaos Synchronization Using A Robust Sliding Mode Observer By Transmitting A Scalar Signal

A New Multiscale Line Detection Approach for Aerial Image with Complex Scene

A Display Order Oriented Scalable Video Decoder

Implementation of Multipoint Video Conference in Software

An Improved SVD-Based Watermarking Technique for Image and Document Authentication

Study on Complex Behavior in Phase-Shifting Full-Bridge ZVS Converter

Uncertainty Management for Estimation in Dynamical Systems

Nonlinear STATCOM Controller using Passivity-Based Sliding Mode Control

Frequency Interval Gramians based Model Reduction

Simultaneous Analysis of Capacitive Coupling and Leakage Noise in Nanometer Scale Circuits

A Simulink-to-FPGA Co-Design of Encryption Module

Analytic Solution of Amplitude Controlled Digital Oscillator Using Multi-Time Variables Technique

Reduced-Dimension Single Data Set Detection Algorithms

Efficient VLSI Design for RNS Reverse Converter Based on New Moduli Set $(2^{n}-1,$ $2^{n}+1,$ $2^{2n+1})$

Online Continues Vietnamese Handwritten Character Recognition Based on Microsoft Handwritten Character Recognition Library

The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.

Asia-Pacific Conference on Circuits and Systems

IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394)

IEEE. APCCAS 1998. 1998 IEEE Asia-Pacific Conference on Circuits and Systems. Microelectronics and Integrating Systems. Proceedings (Cat. No.98EX242)

Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems

Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems

Multiple-Symbol Parallel CAVLC Decoder for H.264/AVC

Content Provider	IEEE Xplore Digital Library
Author	Ya-Nan Wen Guan-Lin Wu Sao-Jie Chen Yu-Hen Hu
Copyright Year	2006
Description	Author affiliation: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei (Ya-Nan Wen; Guan-Lin Wu; Sao-Jie Chen)
Abstract	In this paper, the authors propose a novel high-throughput, ASIC architecture to realize the context-adaptive variable-length decoder (CAVLC) of H.264/AVC baseline profile. The authors conduct a thorough analysis of inherent parallelism of the CAVLC algorithm and identify particular steps that will benefit from parallel computing. In particular, the authors adopt a bit-position VLC decoding approach to decode multiple symbols concurrently in a critical step in CAVLC. This modification leads to almost 40% reduction of clock cycles compared to a straight-forward implementation
Starting Page	1240
Ending Page	1243
File Size	325837
Page Count	4
File Format	PDF
ISBN	1424403871
DOI	10.1109/APCCAS.2006.342387
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-04
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Automatic voltage control Image coding Acceleration Parallel processing Clocks Entropy coding Table lookup Application specific integrated circuits Computer architecture multiple-symbol H.264 entropy coding CAVLC variable length coding
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in