NDLI: An Efficient Realization of the Decision Feedback Equalizer using Block Floating Point Arithmetic

Content Provider	IEEE Xplore Digital Library
Author	Shaik, R. Chakraborty, Mrityunjoy
Copyright Year	2006
Description	Author affiliation: Dept. of E & ECE, Indian Inst. of Technol., Kharagpur (Shaik, R.)
Abstract	An efficient scheme is presented for implementing the decision feedback equalizer (DFE) in block floating point (BFP) format, which permits processing of data over a wide dynamic range at a processor cost marginally higher than that of a fixed point processor. It uses block processing of the input which is block formatted by an appropriate algorithm, taking care so that there is no overflow at the feed forward filter output and also that a uniform BFP representation of the input data vector is available all throughout including the inter-block transition phase. Suitable steps are also taken for block formatting the data used in computation of the feedback filter output, again ensuring no overflow. As the computations involve mostly fixed point based operations, considerable saving in computational complexities is achieved, as against a conventional floating point based realization
Starting Page	1047
Ending Page	1050
File Size	172723
Page Count	4
File Format	PDF
ISBN	1424403871
DOI	10.1109/APCCAS.2006.342268
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-04
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decision feedback equalizers Floating-point arithmetic Field-flow fractionation Filters Dynamic range Intersymbol interference Signal processing algorithms Feeds Electronics packaging Costs
Content Type	Text
Resource Type	Article

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