NDLI: An Implantable SOC Chip for Micro-stimulating and Neural Signal Recording

Content Provider	IEEE Xplore Digital Library
Author	Chua-Chin Wang Chi-Chun Huang Tzung-Je Lee Cheng-Mu Wu Gang-Neng Sung Kuan-Wen Fang Sheng-Lun Tseng Jia-Jin Chen
Copyright Year	2006
Description	Author affiliation: Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung (Chua-Chin Wang; Chi-Chun Huang; Tzung-Je Lee; Cheng-Mu Wu; Gang-Neng Sung; Kuan-Wen Fang; Sheng-Lun Tseng; Jia-Jin Chen)
Abstract	An implantable SOC chip for micro-stimulation and neural signal recording is presented. This work possesses a multi-parameter control protocol to provide different stimulation waveforms, for various pain treatments of muscles and stimulating applications. Additionally, the proposed SOC chip supports several transmission rates of RS232, which in turn provides a flexibility to be integrated in a variety of different applications. Moreover, an IA (instrument amplifier) with CMRR of 120 dB and the stopband attenuation of 38 dB/dec is employed, which is capable of sensing very low voltage (1 to 10 muV) neural signal. The proposed design is implemented using TSMC 2P4M 0.35 mum CMOS process
Starting Page	682
Ending Page	685
File Size	257308
Page Count	4
File Format	PDF
ISBN	1424403871
DOI	10.1109/APCCAS.2006.342099
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-04
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wireless sensor networks Pain Muscles Voltage Protocols Attenuation Circuits Regulators Power generation Signal generators neural signal recording implanltable wireless neural stimulation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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