NDLI: Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion

Content Provider	IEEE Xplore Digital Library
Author	Chia-Chun Tsai Jan-Ou Wu Trong-Yen Lee Rong-Shue Hsiao
Copyright Year	2006
Description	Author affiliation: Dept. of Comput. Sci. & Inf. Eng., Nanhua Univ., Chiayi (Chia-Chun Tsai)
Abstract	In this paper, the authors propose a greedy algorithm to minimize the maximal propagation delay for giving the topology of a multi-source multi-sink bus with RLC delay model. The algorithm minimizes the maximal delay by inserting signal repeaters into the critical path and adjusts their sizes, and repeats the above procedure until no any improvement in delay reduction. Experimental results exhibit that the algorithm can reduce the critical delay of a bus effectively for deep submicron technologies. The average savings in critical delay of RLC-based buses for 0.35mum and 0.18mum technologies are less 5.6% and 4% than that of RC-based buses, respectively, whereas the usages in size of RLC-based buses for 0.35mum and 0.18mum technologies are less 3.2 and 13.2 than that of RC-based buses, respectively. The average errors compared with HSPICE in critical delay of RLC-based buses for 0.35mum and 0.18mum technologies are better 3.53% and 1.09% than that of RC-based buses, respectively. The algorithm is simple but very effective
Starting Page	1285
Ending Page	1288
File Size	4847370
Page Count	4
File Format	PDF
ISBN	1424403871
DOI	10.1109/APCCAS.2006.342398
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-04
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Propagation delay Repeaters Wire Integrated circuit interconnections Delay effects Capacitance Greedy algorithms Superluminescent diodes Clocks Computer science RLC delay model repeater insertion bus
Content Type	Text
Resource Type	Article

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