NDLI: A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication Systems

Content Provider	IEEE Xplore Digital Library
Author	Young-Jae Cho Kyung-Hoon Lee Hee-Cheol Choi Young-Ju Kim Kyoung-Jun Moon Seung-Hoon Lee Seok-Bong Hyun Seong-Su Park
Copyright Year	2006
Description	Author affiliation: Dept. of Electron. Eng., Sogang Univ., Seoul (Young-Jae Cho; Kyung-Hoon Lee; Hee-Cheol Choi; Young-Ju Kim; Kyoung-Jun Moon; Seung-Hoon Lee)
Abstract	This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference preamplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble code correction circuits to optimize power, chip area, and accuracy at 1GS/s. The ADC implemented in a 0.18mum 1P6M CMOS technology shows a signal-to-noise-and-distortion ratio of 30dB and a spurious-free dynamic range of 39dB at 1GS/s. The measured differential and integral nonlinearities of the prototype ADC are within 1.00LSB and 1.25LSB, respectively. The dual-channel ADC has an active area of $4.0mm^{2}$ and consumes 594mW at 1GS/s and 1.8V
Starting Page	339
Ending Page	342
File Size	3615808
Page Count	4
File Format	PDF
ISBN	1424403871
DOI	10.1109/APCCAS.2006.342420
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-04
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Ultra wideband technology CMOS technology Broadband amplifiers Differential amplifiers Power amplifiers Preamplifiers Latches Noise reduction Circuit noise CMOS digital integrated circuits ultra wide band ADC CMOS flash kickback
Content Type	Text
Resource Type	Article

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