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Content Provider | IEEE Xplore Digital Library |
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Author | Bojnordi, Mahdi Nazm Sedaghati-Mokhtari, Naser Omid Fatemi Hashemi, Mahmoud Reza |
Copyright Year | 2006 |
Description | Author affiliation: Sch. of Electr. & Comput. Eng., Tehran Univ. (Mahdi Nazm Bojnordi; Naser Sedaghati-Mokhtari; Omid Fatemi; Mahmoud Reza Hashemi) |
Abstract | Many 2D data processing applications can be simplified and represented by use of 1D operations. Such tools, however, require applying both vertical and horizontal operations to the data blocks. The data transposing units is preferred to be used by the designers rather than applying individual operations for horizontal and vertical directions. Hence, designing a cost efficient and extendible transposing memory is a key issue for these applications. This paper proposes an efficient management strategy for using the SRAM modules in order to make a self-transposing memory architecture (STMA). In addition to its lower cost compared to flip-flop based buffers, the proposed architecture is more than 29% faster than usual SRAM based memory units. Simulations indicate that using the STMA in the H.264/AVC deblocking filter results in 60% speed improvement |
Starting Page | 1438 |
Ending Page | 1441 |
File Size | 210557 |
Page Count | 4 |
File Format | |
ISBN | 1424403871 |
DOI | 10.1109/APCCAS.2006.342472 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2006-12-04 |
Publisher Place | Singapore |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Filters Engines Costs Random access memory Automatic voltage control Hardware Pixel Signal processing algorithms Memory architecture Switches Self-Transposing memory |
Content Type | Text |
Resource Type | Article |
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