NDLI: Optimum repeater insertion to minimize the propagation delay into 32nm RLC interconnect

Content Provider	IEEE Xplore Digital Library
Author	Deschacht, D.
Copyright Year	2011
Description	Author affiliation: LIRMM, UMR Université Montpellier II - CNRS, CC 477, 161 rue Ada, 34 095 Montpellier cedex5 - France (Deschacht, D.)
Abstract	When high speed integrated digital circuits technology scales down from one node to the other as ITRS recommends, a significant gain is obtained on signal speed, consumption and area of CMOS transistors. Nevertheless a specific issue occurs from the 45 nm technology node. The obtained gain on active devices is foiled by an increase of interconnect propagation delays in the Back-End of Line (BEOL). This issue especially concerns relatively long (few hundred of mm) interconnects of the intermediate metal level. By introducing drivers (repeaters) in order to divide long interconnect in shorter sections and choosing optimal drivers sizes, speed can be maximized. This paper proposes a new optimal buffer sizing, and maximum length to be used for repeater networks, to optimize propagation delay for long interconnect of the 32nm technology, by taking into account, for the first time, the input transition time at each stage.
Starting Page	1
Ending Page	4
File Size	858541
Page Count	4
File Format	PDF
ISBN	9781467322881
ISSN	21511233
e-ISBN	9781467322904
e-ISBN	9781467322898
DOI	10.1109/EDAPS.2011.6213729
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-12-12
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit interconnections Metals Repeaters Dielectrics Delay Optimization Propagation delay
Content Type	Text
Resource Type	Article

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