NDLI: A novel VLSI architecture of lum interpolator of H.264 decoder

Content Provider	IEEE Xplore Digital Library
Author	Duo-Li Zhang Xian-Wen Cheng Gao-Ming Du Yu-Kun Song Ming-Lun Gao
Copyright Year	2009
Description	Author affiliation: Institute of VLSI Design, Hefei University of Technology, China (Duo-Li Zhang; Xian-Wen Cheng; Gao-Ming Du; Yu-Kun Song; Ming-Lun Gao)
Abstract	Motion compensation is the most critical part for the performance of H.264 decoder. Through fully analysis of the interpolation algorithm, a symmetry characteristic in the algorithm has drawn our attention. Based on a precise deduction, a new VLSI architecture for motion compensation lum interpolation is presented in this paper. This architecture is based on separated 1-D approach and reuses the horizontal half-sample interpolation 6-tap FIRs and the horizontal vertical half-sample interpolation 6-tap FIRs. Experiment results shows that compared with arithmetic adopting separated 1-D approach referenced, the proposed arithmetic can save 5 6-tap FIRs and 6 eight-bit registers. A H.264 decoder adopting the proposed approch can achieve real-time decoding 30 fps baseline H.264/AVC video with 1080HD resolutions at a clock speed of $100MHz^{1}.$
Starting Page	175
Ending Page	178
File Size	5271361
Page Count	4
File Format	PDF
ISBN	9781424438686
DOI	10.1109/ASICON.2009.5351578
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Decoding Interpolation Automatic voltage control Motion compensation Algorithm design and analysis Arithmetic Costs Finite impulse response filter Symmetric matrices VLSI architecture H.264 lum interpolation separated 1-D
Content Type	Text
Resource Type	Article

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