NDLI: A precise SystemC-AMS model for Charge Pump Phase Lock Loop with multiphase outputs

Content Provider	IEEE Xplore Digital Library
Author	Tao Xu Arriens, H.L. van Leuken, R. de Graaf, A.
Copyright Year	2009
Description	Author affiliation: Circuits and Systems Group, Department of microelectronics&Computer Engineering, Faculty of Electrical Engineering Mathematics and Computer Science, Delft University of Technology, Netherlands (Tao Xu; Arriens, H.L.; van Leuken, R.; de Graaf, A.)
Abstract	SystemC-AMS as an extension of SystemC provides the essential capability to describe a mix-signal heterogeneous system, so that a virtual-prototype model can be generated to help analyze a whole mix-signal system and further guide the circuit design. This paper presents an example of Systemc-ams modeling for a 10 phase 500MHz Charge Pump Phase Lock Loop, including digital models like Phase/Frequency Detector and clock N-divider, and analog models like Charge Pump, Low Pass Filter and Voltage Controlled Oscillator. In order to prove the model's accuracy, the SPICE simulation result from the corresponding CMOS circuits based on the same structure of these models is used for comparison, and PLL Systemc-ams model is $validated^{1}.$
Starting Page	50
Ending Page	53
File Size	3534181
Page Count	4
File Format	PDF
ISBN	9781424438686
DOI	10.1109/ASICON.2009.5351608
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Charge pumps Semiconductor device modeling Circuit synthesis Phase detection Phase frequency detector Clocks Low pass filters Voltage-controlled oscillators SPICE Circuit simulation CMOS SystemC-AMS Charge Pump PLL
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A CMOS charge pump with a novel structure in PLL

A 625 MHz CMOS Phase-locked Loop Used In Lock Detector Application

Differential charge pump circuit for high speed PLL application

Design a 4GHz PLL for wireless receiver

A low noise CMOS phase locked loop

High speed CMOS charge pump circuit for PLL applications using 90nm CMOS technology

Fast-Lock Dual Charge Pump Analog DLL using Improved Phase Frequency Detector

A low jitter wide tuning range phase locked loop with low power consumption in 180nm CMOS technology

Phase Aligned Clock Multiplier

A precise SystemC-AMS model for Charge Pump Phase Lock Loop with multiphase outputs

Similar Documents

A CMOS charge pump with a novel structure in PLL

A 625 MHz CMOS Phase-locked Loop Used In Lock Detector Application

Differential charge pump circuit for high speed PLL application

Design a 4GHz PLL for wireless receiver

A low noise CMOS phase locked loop

High speed CMOS charge pump circuit for PLL applications using 90nm CMOS technology

Fast-Lock Dual Charge Pump Analog DLL using Improved Phase Frequency Detector

A low jitter wide tuning range phase locked loop with low power consumption in 180nm CMOS technology

Phase Aligned Clock Multiplier

A precise SystemC-AMS model for Charge Pump Phase Lock Loop with multiphase outputs