NDLI: A single channel 2GS/s 6-bit ADC with cascade resistive averaging

Content Provider	IEEE Xplore Digital Library
Author	Youtao Zhang Xiaopeng Li Ao Liu Ming Zhang Feng Qian
Copyright Year	2009
Description	Author affiliation: Integrated Circuit Laboratory, Nanjing Electronic Devices Institute, China (Xiaopeng Li; Ao Liu) \|\| National Key Laboratory of Monolithic Integrated Circuits and Modules, Nanjing Electronic Devices Institute, NanJing, China (Youtao Zhang)
Abstract	A single channel 2GS/s 6-bit ADC with cascade resistive averaging is demonstrated in 0.18µm CMOS. The proposed power efficient crossing connection method of averaging resistors has less reference voltage consumed than convention with excellent offset averaging. The peak DNL and INL are measured as 0.26 LSB and 0.21 LSB, respectively. The SNDR and SFDR have achieved 34.2 and 37.5dB, respectively, with 1.22 MHz input signal and 2GS/s. The SNDR and SFDR maintain above 30 and 35dB, respectively, up to1000MHz input signal and 900MS/s. The proposed ADC, including onchip track-and-hold amplifiers and clock buffers, consumes 570 mW from a single 1.8V supply while operating at $2GS/s^{1}.$
Starting Page	195
Ending Page	198
File Size	3355876
Page Count	4
File Format	PDF
ISBN	9781424438686
DOI	10.1109/ASICON.2009.5351501
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches Preamplifiers Broadband amplifiers Resistors Interpolation Energy consumption Bandwidth Laboratories Capacitance Voltage interpolation Analog-to-digital conversion offset averaging flash
Content Type	Text
Resource Type	Article

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