NDLI: VLSI Implementation of CAVLC Decoder for H.264/AVC Video Decoding

Content Provider	IEEE Xplore Digital Library
Author	Chen Guanghua Wan Fenfang Ma Shiwei
Copyright Year	2007
Description	Author affiliation: Minist. of Educ. & Microelectron. R&D Center, Shanghai Univ., Shanghai (Chen Guanghua; Wan Fenfang; Ma Shiwei)
Abstract	This paper presents an efficient method of the contest- based adaptive variable length code (CAVLC) decoder for H.264/AVC standard. In the proposed design, according to the regularity of the codewords, the first 1 detector is used to solve the problem that the traditional method of table- searching has low efficiency. Considering the relevance of the data used in the process of RunBefore's decoding, arithmetic operation is combined with FSM, which achieves higher decoding efficiency. The simulation result shows that the decoder can decode the coded stream of transform coefficients in each block. Moreover, it can decode every syntax element in one clock cycle. When the proposed design is synthesized at clock constraint of 100 MHz, the synthesis result shows that the design costs 9600 cells under a 0.25 mum CMOS technology, which meets the demand of real time decoding in H.264/AVC standard.
Starting Page	1
Ending Page	3
File Size	221631
Page Count	3
File Format	PDF
ISBN	1424412528
DOI	10.1109/HDP.2007.4283628
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-26
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Very large scale integration Automatic voltage control Detectors Arithmetic Code standards Clocks Costs CMOS technology Laboratories decode H.264/AVC CAVLC
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

VLSI implementation of CAVLC decoder with power Optimized for H.264/AVC video decoding

High performance VLSI implementation of CAVLC decoder of H.264/AVC for HD transmission

High Performance Architecture Design of CAVLC Encoder in H.264/AVC

A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding

An Efficient Implementation of CAVLC for H.264/AVC

Combined CAVLC Decoder, Inverse Quantizer, and Transform Kernel in Compact H.264/AVC Decoder

Low complexity and high throughput VLSI architecture for AVC/H.264 CAVLC decoding

An area reduction scheme for the H.264/AVC CAVLC encoder

Power-efficient VLSI implementation of bitstream parsing in H.264/AVC decoder

VLSI Implementation of CAVLC Decoder for H.264/AVC Video Decoding

Similar Documents

VLSI implementation of CAVLC decoder with power Optimized for H.264/AVC video decoding

High performance VLSI implementation of CAVLC decoder of H.264/AVC for HD transmission

High Performance Architecture Design of CAVLC Encoder in H.264/AVC

A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding

An Efficient Implementation of CAVLC for H.264/AVC

Combined CAVLC Decoder, Inverse Quantizer, and Transform Kernel in Compact H.264/AVC Decoder

Low complexity and high throughput VLSI architecture for AVC/H.264 CAVLC decoding

An area reduction scheme for the H.264/AVC CAVLC encoder

Power-efficient VLSI implementation of bitstream parsing in H.264/AVC decoder

VLSI Implementation of CAVLC Decoder for H.264/AVC Video Decoding