NDLI: Transaction level model of NoC based on SystemC

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Keynote speech index

2007 7th International Conference on ASIC

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ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549)

2nd International Conference on ASIC

Transaction level model of NoC based on SystemC

Content Provider	IEEE Xplore Digital Library
Author	Jian Wang Hong Wang Zhi jia Yang
Copyright Year	2009
Description	Author affiliation: Key laboratory of communication and control, Shenyang Institute of Automation, Chinese Academy of Sciences, Liaoning, Shenyang 110016, China (Jian Wang; Hong Wang; Zhi jia Yang)
Abstract	This paper presents a transaction-level on-chip communication network model, including routers and links, which can be easily employed in a system-level system-on-chip simulation framework for early functional verification and architecture analysis. The model is capable of providing NoC's latency and throughput information during simulating process and developed in SystemC to achieve high simulation $speed^{1}.$
Starting Page	97
Ending Page	100
File Size	3882610
Page Count	4
File Format	PDF
ISBN	9781424438686
DOI	10.1109/ASICON.2009.5351599
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Network-on-a-chip System-on-a-chip Natural languages Laboratories Automatic control Communication system control Analytical models Delay Throughput Control systems SystemC network on chip transaction-level model
Content Type	Text
Resource Type	Article

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