NDLI: An experimental extracted model for latchup analysis in CMOS process

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2nd International Conference on ASIC

An experimental extracted model for latchup analysis in CMOS process

Content Provider	IEEE Xplore Digital Library
Author	Ye Li Xiaohan Gong Weiwei Xu Zhiliang Hong Killat, D.
Copyright Year	2009
Description	Author affiliation: University of technology, Cottbus, Germany (Killat, D.) \|\| State Key Laboratory of ASIC and System, Fudan University, Shanghai, China (Ye Li; Xiaohan Gong; Weiwei Xu; Zhiliang Hong)
Abstract	The latchup phenomenon is analyzed theoretically. A practical analytical model derived from Ebers-Moll formulations is proposed to analyze, simulate, and predict latchup, with favorable legitimacy and flexibility. The model parameters are extracted on 0.25um CMOS process from experiments. The extracted model can predict latchup successfully in circuit level when applied in $SPICE^{1}.$
Starting Page	1035
Ending Page	1038
File Size	2943745
Page Count	4
File Format	PDF
ISBN	9781424438686
DOI	10.1109/ASICON.2009.5351514
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device modeling CMOS process Analytical models Thyristors Voltage Predictive models SPICE Variable structure systems MOSFET circuits Circuit simulation switching converter latchup Coupled BJT model Ebers-Moll model thyristor power MOSFET
Content Type	Text
Resource Type	Article

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