NDLI: A 2.84W 16port Switch ASIC for high performance computing systems

Content Provider	IEEE Xplore Digital Library
Author	Hua Shen Ding-shan You Like Liu Jia Yang Xiao-xiao Jiang
Copyright Year	2009
Description	Author affiliation: ASIC Group, National Center of Intelligent, Computing Systems (NCIC), Institute of Computing Technologies, Chinese Academy of Sciences, China (Hua Shen; Ding-shan You; Like Liu) \|\| NCIC, China (Jia Yang; Xiao-xiao Jiang)
Abstract	The chip's structure, design trade-off, and physical implementation with power optimization of a 2.84W Switch ASIC, which is targeted for large scale parallel computing systems, are introduced in this paper. The chip supports not only multi-layer, multi-function packet switching with high throughput and low latency, but also provides advanced global barrier process accelerating between its 16 full-duplex ports. At 156.25 Mhz, the chip has 83.2ns zero-load latency, 80Gbps port-switching and 240Gbps internal packet switching capacity with port's data throughput at 2×2.5Gbps. The ASIC has been taped-out with 0.18um/6Metal CMOS technology, and has about 20 million transistors; 12.39 mm × 12.39 mm die size; with 1053 pin flip-chip package. The first pass silicon of this Switch ASIC has successfully passed DFT, functional and system level testing.
Starting Page	54
Ending Page	57
File Size	5546886
Page Count	4
File Format	PDF
ISBN	9781424438686
DOI	10.1109/ASICON.2009.5351609
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches Application specific integrated circuits High performance computing Packet switching Throughput Delay CMOS technology Design optimization Large-scale systems Parallel processing DFT Switch Low Power Timing Design
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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