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Content Provider | IEEE Xplore Digital Library |
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Author | Chi-Hsien Lin Yen-Ying Huang Shu-Rung Li Yuan-Pu Cheng Shyh-Jye Jou |
Copyright Year | 2009 |
Description | Author affiliation: Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan R.O.C. (Chi-Hsien Lin; Yen-Ying Huang; Shu-Rung Li; Yuan-Pu Cheng; Shyh-Jye Jou) |
Abstract | A low jitter phase-lock-loop (PLL) and a proposed spread-spectrum clock method for Serial ATA with phase rotation is presented. The low jitter PLL uses error amplifier to resolve the current mismatch in charge pump and the $3^{rd}$ order loop filter is adopted to reduce the reference spur. A passive resistance is presented in our design to reduce the KVCO. Our spread spectrum clock generator (SSCG) for Serial ATA specification is down spread 5000 ppm with a triangular waveform and the modulation frequency is 30∼33KHz. Spread-spectrum technique using PLL with a Δ Σ modulator and phase rotation algorithm is reported. The proposed circuit has been designed in a 90-nm CMOS process. The non-spread spectrum clocking has a peak to peak jitter of 512fs and consumes 5.87mW at 1.4GHz. The EMI reduction is about 19.24dB. |
Starting Page | 387 |
Ending Page | 390 |
File Size | 7354031 |
Page Count | 4 |
File Format | |
ISBN | 9781424438686 |
DOI | 10.1109/ASICON.2009.5351414 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2009-10-20 |
Publisher Place | China |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Clocks Spread spectrum communication Jitter Phase locked loops Charge pumps Filters Frequency modulation Phase modulation Circuits CMOS process SSCG PLL serial ATA EMI |
Content Type | Text |
Resource Type | Article |
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