NDLI: A fully pipelined CABAC coder using syntax element instructions driving

Content Provider	IEEE Xplore Digital Library
Author	Shenggang Chen Shuming Chen Xi Ning
Copyright Year	2009
Description	Author affiliation: National University of Defense Technology, Changsha, Hunan 410073 China (Shenggang Chen; Shuming Chen; Xi Ning)
Abstract	Context-based Adaptive Binary Arithmetic Coder (CABAC) is an essential part in the H.264 main profile video encoder to generate final bitstream. With the development of large-scale parallel H.264 encoder and the high definition video requirement, it increasingly poses a bottleneck in the video encoding path of the parallel encoders. This paper proposes a fully pipelined hardware CABAC coder to speed up the bitstream generation, which is suitable for accelerating a node processor in a manycore chip. The coder employs a CPU-like execution style and using the Syntax Elements Instructions (SEI) to drive the pipeline. Synthesis results with SIMC 0.13um technology show that with an area of 3.21K logic gates, 3.5K RAM bits and 34.375K ROM bits, this design can achieve a high throughput of 590Mbps, basically supporting the real-time HD video $coding^{1}.$
Starting Page	167
Ending Page	170
File Size	2216136
Page Count	4
File Format	PDF
ISBN	9781424438686
DOI	10.1109/ASICON.2009.5351580
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	High definition video Arithmetic Large-scale systems Encoding Hardware Acceleration Pipelines Logic gates Logic design Read only memory hardware accelerator CABAC pipeline
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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