NDLI: Advancing Moore's law: Challenges and opportunities

Content Provider	IEEE Xplore Digital Library
Author	Peng Bai
Copyright Year	2009
Description	Author affiliation: Intel, USA (Peng Bai)
Abstract	Moore's law has been the guiding principle of silicon CMOS technology scaling for four decades. Transistor density has been doubled every two years in Intel microprocessors since early '70. Intel's latest dual core Itanium® 2 server chip has deployed 1.72 billion transistors vs. 2,250 transistors in the 4004 processor introduced in 1971. Same density improvement trends can be found in memory and other ASIC products as well. The remarkable progress in packing more functionality, complexity, and performance into a single silicon chip could have not been achieved without numerous innovations in IC manufacturing technologies, lithography, transistors, interconnects and packaging. In this presentation, I will provide a review of most critical process technology innovations in the last decade, including advanced lithography, strained silicon transistors, high k/metal gate transistors, Cu metallization, and low k ILD. The last decade of Moore's law has been characterized by significant differences, compared to the first three decades of silicon scaling, in the types of technical challenges and innovations that are required to advance Moore's law. The insight into the challenges and opportunities will help guide advancing Moore's law into the future.
Starting Page	7
Ending Page	8
File Size	1775972
Page Count	2
File Format	PDF
ISBN	9781424438686
DOI	10.1109/ASICON.2009.5351292
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Moore's Law Silicon Transistors Technological innovation CMOS technology Lithography Microprocessors Application specific integrated circuits Manufacturing Integrated circuit packaging
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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