NDLI: A low dropout regulator with over current reminder circuits

Please wait, while we are loading the content...

2013 IEEE 10th International Conference on ASIC

2011 9th IEEE International Conference on ASIC

2009 IEEE 8th International Conference on ASIC

A LUT-based VRC model for random logic function evolution

Low power design of vlsi circuits and systems

A multi-channel, area-efficient, audio sampling rate interpolator

Low-power MCML circuit with sleep-transistor

Architecture design of variable lengths instructions expansion for VLIW

A systolic architecture with linear space complexity for longest common subsequence problem

SFG realization of wavelet filter using switched-current circuits

Design of a high reliable L1 data cache with redundant cache

Switching activity calculation of VLSI adders

A precise SystemC-AMS model for Charge Pump Phase Lock Loop with multiphase outputs

A 2.84W 16port Switch ASIC for high performance computing systems

Design of multi-valued double-edge-triggered JK flip-flop based on neuron MOS transistor

Trends of terascale computing Chips in the next ten years

A high power efficiency reconfigurable processor for multimedia processing

DReNoC: A dynamically reconfigurable computing system based on network-on-chip

An efficient parallel instruction execution method for VLIW DSP

Dynamic context management for coarse-grained reconfigurable array DSP architecture

A reconfigurable architecture specific for the butterfly computing

Optimal-Partition Based code compression for embedded processor

$T^{2}-$ TAM:Reusing infrastructure resource to provide parallel testing for NoC based Chip

Transaction level model of NoC based on SystemC

An energy-aware heuristic constructive mapping algorithm for Network on Chip

Speedup analysis of data-parallel applications on Multi-core NoCs

Uniform routing architecture for FPGA with embedded IP cores

Mixed optimization method in design of FC-2

Partially reconfigurable interconnection network for dynamically reprogrammable resource array

Fast configuration architecture of FPGA suitable for bitstream compression

VLSI implementation of high-speed SHA-256

Low-cost reconfigurable VLSI implementation of the SMS4 and AES algorithms

The simulation model and ASIC implementation of a random bit source circuit

HMF unit: A key element in dynamic dataflow ASIC

VLSI architecture of a low complexity face detection algorithm for real-time video encoding

Unified low cost crypto architecture accelerating RSA/SHA-1 for security processor

The research and design of parallel instruction targeted at substitution box

Design and FPGA implementation of 3DES against Power Analysis Attacks for IC bankcard

Analysis of adaptive algorithm to power aware design for H.264/AVC integer motion estimation engine in HDTV application

A fully pipelined CABAC coder using syntax element instructions driving

Pre-processor of the region-of-interest based H.264 encoder for low power application

A novel VLSI architecture of lum interpolator of H.264 decoder

A Comparative Study of subword parallel adders for multimedia applications

Parallel enhanced low design effort H.264/AVC fractional motion estimation engine for Super Hi-Vision application

Three images blending engine supporting multicolor formats, various color depths with small-gate size and high-quality image for SOC design

A reconfigurable architecture for DWT and IDWT in JPEG2000

An efficient verification and test scheme for media broadcasting demodulator

A high-throughput cost-effective ASIC implementation of the AES Algorithm

A fast-lock digital delay-locked loop controller

Performance evaluation of the memory hierarchy design on CMP prototype using FPGA

Power-aware FPGA packing algorithm

High computing-intensive array system design and hardware implement

Tradeoff design for analog integrated circuits via geometric programming

Clocked storage elements robust to process variations

Research and implementation of parallel and reconfigurable MICKEY algorithm

A power and area efficient architecture of convolver based on ram

A design of level interface for CMP based Cache system

Scalable and unified hardware architecture for montgomery inversion computation in GF(p) and $GF(2^{n})$

Design and optimization on reconfigurable butterfly core for a real-time FFT processor

Design of low-power Complementary Pass-Transistor and ternary adder based on multi-valued switch-signal theory

A Look-Up-Table Based Differential Logic to counteract DPA attacks

A parallel intra prediction architecture for H.264 video decoding

DM-SIMD: A new SIMD predication mechanism for exploiting superword level parallelism

A 1Gsample/Sec non-recursive sharpened cascaded integrator-comb filter with 70 dB alias rejection and 0.003 dB droop in 0.18-µm CMOS

Trade-offs in the design of a universal sensor interface chip

Design and implementation of configurable extract instructions targeted at stream cipher processing

Single-phase adiabatic flip-flops and sequential circuits with power-gating scheme

Design of ternary adiabatic T-operation circuit based on the theory of three essential circuit elements

Least operation traversal method applied in optimization of logic circuits

High performance and low latency mapping for neural network into network on chip architecture

An improved edge-adaptive image scaling algorithm

A data-flow graph generation algorithm for a coarse-grained reconfigurable processor

Data compression and the 8×8 integer transform

A weighted statistical analysis of DPA attack on an ASIC AES implementation

Efficient hardware IP control and simulation with LabVIEW

A novel architecture of vision chip for fast traffic lane detection and FPGA implementation

CMOL cell assignment based on dynamic interchange

A 2.4GHz non-contact biosensor system for continuous vital-signs monitoring on a single PCB

A technique of data streams speculation for heterogeneous MC-DSPs

Power analysis resistant AES crypto engine design and FPGA implementation for a network security co-processor

Blind separation algorithm for microphone array based on recursive neural network

Neural signal electronics bridge integrated circuit

Design and experimental research on shallow water volume reverberation signal acquisition system

Architectural integration of RSA accelerator into MIPS processor

Quality of service routing algorithm in the torusbased network on chip

A switched Hall IC for automotive electronic applications

Design of on-chip image processing based on APB bus with CMOS image sensor

Automatic parallelization experiments on 16PE NOC based MPSOC

Design and FPGA implementation of JAVA CARD coprocessor for EMV compatible IC bankcard

A low-cost custom HF RFID system for hand washing compliance monitoring

A joint mode detection and coarse symbol synchronization scheme for DVB-H

An UHF RFID transponder for ISO 18000-6B

A new DOA estimation method for uncorrelated and coherent sources under nonstationary noise fields

A novel programmable ultra-wideband transmitter

An multi-rate LDPC decoder based on ASIP for DMB-TH

Design and implementation of a security-enhanced baseband system for UHF RFID tag

Low-complexity architecture of RS decoder for CMMB system

A cost efficient LDPC decoder for DVB-S2

High-reliable multi-level phase change memory with bipolar selectors

A pure logic CMOS based low power non-volatile random access memory for RFID application

Flow field plate of micro fuel cell fabrication in UV-nanoimprint lithography

Thermal stress analysis of the microtoroid under CO2 laser

Improved thermal stability of power SiGe heterojunction bipolar transistor with novel emitter structure

Investigation into trap-assisted tunneling drain leakage current in NMOSFETs

An experimental extracted model for latchup analysis in CMOS process

A novel MTJ-based register

Effect of refractive index of dielectric on transmission properties for metal/dielectric/metal photonic crystal

The gate-bias influence for ESD characteristic of NMOS

The size optimize of DCVSPG logic

A single channel 2GS/s 6-bit ADC with cascade resistive averaging

A 600-msample/s, 25-mW, 6-bit folding and interpolating ADC in 0.13µm CMOS

Notice of Violation of IEEE Publication Principles
New architecture of low voltage sigma-delta ADC

A 1-V 32-µW 13-bit CMOS Sigma-Delta A/D converter for biomedical applications

An undersampling 14-bit cyclic ADC

A 3.3mw 91dB SNR sigma-delta modulator in 0.18μm CMOS process

High speed and low power ADC design with dynamic analog circuits

A novel digital calibration with low complexity for pipelined ADC

3.4GS/s 3 bit phase digitizing ADC and DAC for DRFM

Study of Q factor and loop delay effects of a continuous-time Δ Σ AD modulator

A 14-bit successive-approximation AD converter with digital calibration algorithm

A bidirectional overflow digital correction algorithm with a single bit redundancy used in the pipeline A/D converters

A mixed-signal calibration technology for the pipeline A/D converter

A low noise class-AB amplifier for voice communication

DC photocurrent rejection of high transimpedance gain preamplifier in infrared wireless optical receiver

Design of low-voltage high performance CMOS-Current feedback amplifier using indirect feedback compensated Op-Amp

Design of an inductorless 3–10GHz SiGe HBT low-noise amplifier

Design of RF amplifier with tunable active inductor

A 1.5 GHz linear-in-dB Variable Gain Amplifier with process and temperature tracking in 0.18-µm CMOS

A new robust capacitance mis-match measurement for analog/mixed-signal applications

A low power CMOS Mixed-Integrator-Based continuous-time filter

CMOS $4^{th}-order$ gm-c low-pass filter with wide tuning range in high frequency

Tuning of a capacitorless bandpass biquad through sequentially trained ANN

A single-event transient hardened phase-locked loop in 0.18 µm CMOS process

A PSO-based tuning of a capacitorless current-mode bandpass biquad

An LO power distribution network design for integrated 60-GHz transceiver on chip

Effect of Dummy fills on characteristics of passive devices in CMOS millimeter-wave circuits

A low power CMOS bandgap voltage reference with enhanced power supply rejection

A switched-reset 300e ENC 10mW readout ASIC in 180nm CMOS for CdZnTe particle detector

A double-scroll based true random number generator with power and throughput adjustable

A low-noise CMOS readout circuit at low frequency for MEMS capacitive accelerometers

An 0.35μm/ CMOS 2.4Gb/s LVDS for high-speed DAC

A high efficiency CMOS charge pump for low voltage operation

Analysis and design of high power supply rejection LDO

A low breakdown-voltage charge pump based on Cockcroft-Walton structure

High efficiency Autonomous Controlled Cascaded LDOs for Green Battery system

A built-in self-test high-current LED driver

A new layout method to improve the thermal stability of Multi-finger power HBT

Design of highly-efficient wideband RF polar transmitters using Envelope-Tracking (ET) for mobile WiMAX/Wibro applications

A CMMB mobile TV tuner frontend with integrated RSSI for dual-band applications

A switched-inductor based VCO with an ultra-wideband tuning range of 87.6 %

A 15-µs fast-locking frequency synthesizer for reconfigurable wireless systems

High linearity voltage-controlled oscillator

A fully integrated broadband direct-conversion receiver RFIC for satellite tuner

A 2.45GHz CMOS power amplifier with high linearity

A spread spectrum clock generator with phase-rotation algorithm for 6Gbps clock and data recovery

A 0.18 μm CMOS programmable interference canceller for cognitive radio front-end

A 1.8V CMOS polar transmitter front-end for 900MHz EDGE system

Development and production of ZCS soft switching converter-based gate driver IC

A high efficiency filter-less class-D audio power amplifier

A synchronous boost regulator with PWM/PFM mode operation

A low spur charge pump in 0.35µm SiGe process for PLL

A sub-1V 115nA 0.35µm CMOS voltage reference for ultra low-power applications

2.4 GHz Doherty power amplifier with on-chip active balun design

Digital static calibration technology used for 16-bit DAC

A novel 0.72–6.2GHz continuously-tunable ΔΣ fractional-N frequency synthesizer

A low dropout regulator with over current reminder circuits

A sample/hold circuit for 80MSPS 14-bit A/D converter

Single-inductor dual-output converter with dynamic power distribution

CCCII and CCII based universal current-mode filter with tunable frequency

A simple parameter extraction method for on-chip inductors

A novel building block: universal current conveyor

A low power self-sampling IF FSK receiver

A nonlinear phase frequency detector for fast-lock phase-locked loops

A parallel-amplification parallel-summation logarithmic amplifier for UHF RFID reader

Design of parallel backlight LED driver IC

Design of compensation circuits for quasi-resonant PWM controllers

A constant-gain time-amplifier with digital self-calibration

A 2.4-GHz low-IF front-end receiver in 0.18-µm CMOS for IEEE 802.15.4 WPAN applications

An ultra low power sigma-delta modulator for hearing aid with double-sampling

A 760mV CMOS voltage reference with mobility and subthreshold slope compensation

Process-insensitive general purpose rail-to-rail operational amplifier using unity-size transistors

Design of a 2.5Gbps Clock-Data Recovery circuit in 0.18um standard CMOS process

A novel fast-settling ADPLL architecture with frequency tuning word presetting and calibration

Design of novel bootstrap driver used in high power BUCK converter

Design of a noise-canceling differential CMOS LNA for 3.1–10.6 GHz UWB receivers

True single-phase energy recovery flip-flop for low-power application

A 200MHz low-power direct digital frequency synthesizer based on mixed structure of angle rotation

0.5 V 1.3 GHz voltage controlled ring oscillator

A zero-ESR stable adaptively biased low-dropout regulator in standard CMOS technology

Design of 16-bit 400MSPS current steering D/A converter

Practical tuning of an OTA-C bandpass biquad via recurrent geometric programming

Stochastic inductance model of OTA-based inductor

Design of common gate UWB LNA in CMOS

Battery-less piezoceramics mode energy harvesting for automobile TPMS

Novel method of analog circuit schematic synthesis

A jitter measurement circuit based on dual resolution vernier oscillator

Multi-classifier fusion approach based on data clustering for analog circuits fault diagnosis

Hierarchical SoC testing scheduling based on the ant colony algorithm

Novel TSC CMOS circuit

Full coverage location of logic resource faults in A SOC co-verification technology based FPGA functional test environment

Power noise analysis acceleration technique by linear programming

Effectiveness analysis of low power technique of dynamic logic under temperature and process Variations

Variation RLC model of interconnect based on weibull distribution

Surface-potential-based analysis of bias-dependent series resistance in LDD MOSFET

DCCB and SCC based fast circuit partition algorithm for parallel SPICE simulation

An improved resource allocation algorithm for testability

Architecture of SystemC based emulator for ReMAP

The verification of the substrate mathematics model and optimization of the substrate noise canceling technique in mixed signal ICs

Multi-voltage and level-shifter assignment driven floorplanning

A new electrothermally-aware methodology for full-chip temperature optimization

Design of SoC verification platform based on VMM methodology

Transistor permutation for better transistor chaining

Convex-cost flow based redundant-via insertion with density-balance consideration

Design and implementation of MCU chip for automobile TPMS

Formal verification of mixed-signal circuits using extended PSL

Pin assignment for wire length minimization after floorplanning phase

Congestion-driven floorplanning based on two-stage optimization

Template-based compilation for coarse-grained reconfigurable processor

Formal verification of full-wave rectifier: A case study

SystemVerilog-based verification environment using SystemC custom hierarchical channel

Asynchronous dual-mode buck converter design with protection circuits in 0.13µm CMOS process for battery applications

An introduction to assertion-based verification

PAC Duo SoC performance analysis with ESL design methodology

Designing WISHBONE to AMBA Wrapper

Efficient floor-planning methodology for the Jasper Forest SoC on a 45 nanometer process

A study and design of CMOS H-Tree clock distribution network in system-on-chip

Analysis and design of a fully integrated SoC for UHF RFID reader in CMOS technology

Design and implementation of an advanced DMA controller on AMBA-based SoC

Framework for statistical analysis of homogeneous multicore power grid networks

The design of a sub-nanojoule asynchronous 8051 with interface to external commercial memory

Semi-distributed scheduling for flexible codeword assignment in a CDMA Network-on-Chip

A super low power MICS band receiver in 65 nm CMOS for high resolution epi-retinal prosthesis

An application-specific buffer allocation algorithm for network-on-chip

Implementation and evaluation of a heterogeneous multicore SoC

A 290-µW 25-kHz continuous-time delta-sigma modulator for acoustic sensor networks

A low noise and highly linear wideband CMOS RF front-end circuits for digital TV tuners

A low power, wide range VCO with automatic amplitude calibration loop

A Common Gate mixer with transconductance nonlinearity cancellation

Millimeter-wave CMOS circuits for a high data rate wireless transceiver

A 2.4 GHz wireless transmitter front-end for endoscopy capsule system

All digital wireless transceiver using modified BPSK and 2/3 sub-sampling technique

A low power high date rate ASK IF receiver

Digital OFDM transmitter architecture and FPGA design

Implementation of a high-speed parallel Turbo decoder for 3GPP LTE terminals

High-speed Reed-Solomon errors-and-erasures decoder design with burst error correcting

An area-efficient and degree-computationless BCH decoder for DVB-S2

A flexible architecture for multi-standard LDPC decoders

Design and implementation of channel coding for underwater acoustic system

Implementation of LDPC decoder for 802.16e

An area efficient multi-mode architecture for reed-solomon decoder

Design of new training sequence and estimation scheme for frequency dependent I/Q imbalance in MB-OFDM based UWB systems

Design and implementation of a multi-mode interleaver/deinterleaver for MIMO OFDM systems

A low-power 4K point FFT processor for CMMB OFDM receiver system

Area minimization of MPRM circuits

A highly efficient inverse transform architecture for multi-standard HDTV decoder

A novel synchronization scheme for OFDM-based CMMB receivers

Low-voltage and high-speed FPGA I/O cell design in 90nm CMOS

A mobile UHF RFID reader with high linearity receiver

A memory-efficient LUT-based AM/AM digital predistortor for UHF RFID reader

An optimized ΔΣ fractional-N frequency synthesizer for CMOS UHF RFID reader

High efficiency CMOS rectifier circuits for UHF RFIDs using Vth cancellation techniques

A two-stage wake-up circuit for semi-passive RFID tag

A low-power analog front end of passive UHF RFID tag IC for EPC™ C1G2

Development of CMOS UHF RFID modulator and demodulator using DTMOST techniques

A self-testing assisted pipelined-ADC calibration technique

Output test compression for compound defect diagnosis

Wireless built-in self-repair architectures for embedded RAMs

A unified test and debug platform for SOC design

A circuit failure prediction mechanism (DART) for high field reliability

Analysis technique for systematic variation over whole shot and wafer at 45 nm process node

F-scan: An approach to functional RTL scan for assignment decision diagrams

ISTA: An embedded architecture for post-silicon validation in processors

Signature-based testing for adaptive digitally-calibrated pipelined analog-to-digital converters

Probability of calculation failures by soft errors in an embedded processor core

Automatic configuration generation for a SOC co-verification technology based FPGA functional test system

A response compactor for extended compatibility scan tree construction

Soft error filtered and hardened latch

A scan chains combined-balance strategy for hierarchical SoC DFT

Prospects for variation tolerant SRAM circuit designs

A 90-nm CMOS embedded low power SRAM compiler

Low-area 1-kb multi-bit OTP IP design

Dynamic property test of a novel high g microaccelerometer

A novel preamplifier for MEMS microphone

Potential-induced surface stress change during the electrochemical reaction

Design and Simulation of a SAW Filter and a new approach for bandwidth's tuning

Large-scale analog/RF performance modeling by statistical regression

Accelerating PCG power/ground network solver on GPGPU

Multicore processor cluster based sleep transistor sizing considering delay profile

Characterization of WID delay variability using RO-array test structures

A compact analytical model for multi-island single electron transistors

Verilog-A based implementation for coupled model of single event transients in look-up table technique

Modeling of layout-dependent STI stress in 65nm Technology

An equivalent lumped-circuit model for on-chip symmetric intertwined transformer

On-chip spiral inductors synthesis by moving leastsquares approximation

Implementation of high-speed verification platform based on emulator for ReDSP and ReMAP

Enhance SAT conflict analysis for model checking

An efficient FPGA packing algorithm based on simple dual-output basic logic elements

Case study: Functional verification of a reconfigurable systolic array using truss

Trilobite: A Natural Modeling Framework for Processor Design Automation System

The chip Verification method based on memory monitoring

Power-efficient and fault-tolerant circuits and systems

Architecture level thermal modeling for multi-core systems using subspace system method

On VLSI statistical timing analysis and optimization

Efficient modeling of spatial correlations for parameterized statistical static timing analysis

Layout optimizations for double patterning lithography

Fast FPGA placement algorithm using Quantum Genetic Algorithm with Simulated Annealing

Redundant via allocation for layer partition-based redundant via insertion

A heuristic method for module sizing under fixed-outline constraints

A New FPGA placement algorithm for heterogeneous resources

Floorplan and Power/Ground network co-design using guided incremental floorplanning

Thermal via planning aware force-directed floorplanning for D ICs

Coupling noise analysis technique using random walks

Recent advance in computational prototyping for analysis of high-performance analog/RF ICs

Solving dispersive media using PLRC-WCS FDTD method

The minimum delay calculation methods in hybrid timing analysis

Random walk algorithm for large thermal RC network analysis

A proposal for a capture method of low power design intent

Power aware design for next generation's Many Cores computing platforms

Advances in CAD for low power design

Multi-gate-length versus dual-gate-length biasing for active mode leakage power reduction: Benchmarking and modeling

Geometry optimization of SiGe HBTs for noise performance of the monolithic Low noise amplifier

A novel dual SCR device for ESD protection

Quantum-mechanical study on the electron effective mobility of surrounding-gate nMOSFETs

VLSI design of resource shared complex-QMF bank for HE-AAC decoder

Terahertz CMOS circuit design and applications for ultra-high data rate (≫100Gbps) communication

How to achieve ultra low power video processing?

Future directions for RF IC design in silicon microelectronic technologies

Silicon-on-Clothes (SoC) and its healthcare applications

Advancing Moore's law: Challenges and opportunities

Designer's Issues in 3D IC

Assertion-Based Verification

High speed DDR memory interface design

Maximizing Lithium battery life safely and inexpensively when charging portable devices

Scan design and DFT practices

Introduction to SystemVerilog and SystemC

Introduction to C-based high level synthesis

ASIP (Application Specific Instruction-set Processors) design

Keynote speech index

2007 7th International Conference on ASIC

2005 6th International Conference on ASIC

ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549)

2nd International Conference on ASIC

A low dropout regulator with over current reminder circuits

Content Provider	IEEE Xplore Digital Library
Author	Wang Yong-sheng Li Rui-xuan Yu Ming-yan Lai Feng-chang
Copyright Year	2009
Description	Author affiliation: Micro-electronics Center of Harbin institute of technology, China (Wang Yong-sheng; Li Rui-xuan; Yu Ming-yan; Lai Feng-chang)
Abstract	A low voltage, low dropout (LDO) regulator with an over current reminder circuit is proposed in this paper. Based on SMIC 0.18µm mix signal CMOS process, the circuit is able to drive a load up to 120mA, and it can give an over current warning to the customer when the load current is over 120mA, and when the load current drops down to 110mA the warning will be recalled. By using the pole-zero tracking frequency compensation, the ripple of the output voltage between 28mV∼30mV when a current pulse draws-out from the $LDO^{1}.$
Starting Page	1089
Ending Page	1092
File Size	2902265
Page Count	4
File Format	PDF
ISBN	9781424438686
DOI	10.1109/ASICON.2009.5351389
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Regulators Circuits Frequency Protection Stability Low voltage Energy management Power system management Immune system Poles and zeros pole-zero tracking frequency compensation low dropout (LDO) regulator over current reminder circuit
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in