NDLI: Fast FPGA placement algorithm using Quantum Genetic Algorithm with Simulated Annealing

Content Provider	IEEE Xplore Digital Library
Author	Xiao Guo Teng Wang Zhihui Chen Lingli Wang Wenqing Zhao
Copyright Year	2009
Description	Author affiliation: State Key Laboratory of ASIC & System, Fudan University, Shanghai 201203, China (Xiao Guo; Teng Wang; Zhihui Chen; Lingli Wang; Wenqing Zhao)
Abstract	Field-Programmable Gate Array (FPGA) attracts more and more attentions in the digital-design field for its excellent features such as reconfiguration and fast time to market. But the implementation of FPGA is restricted by its hardware framework and the CAD software. This paper proposes Quantum Genetic Algorithm with Simulated Annealing (QGASA) as a hybrid FPGA placement algorithm, which combined the advantage of the fast global search ability of QGA and local adjusting ability of Simulated Annealing (SA) algorithm. The experimental results are compared with the state-of-the-art placement tool Versatile Place and Route (VPR) by running the MCNC benchmark circuits. The results show that the path-timing driven cost of QGASA is similar to VPR, but the overall CPU time is reduced by 70%.
Starting Page	730
Ending Page	733
File Size	1516000
Page Count	4
File Format	PDF
ISBN	9781424438686
DOI	10.1109/ASICON.2009.5351309
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Genetic algorithms Simulated annealing Quantum computing Logic circuits Circuit simulation Central Processing Unit Design automation Wiring Partitioning algorithms congestion-avoidance FPGA placement QGASA path-timing driven
Content Type	Text
Resource Type	Article

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