NDLI: Reaching the limits of CMOS technology

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Reaching the limits of CMOS technology

Electrical performance of chip-on-chip modules

Modeling, simulation, and design methodology of the interconnect and packaging of an ultra-high speed source synchronous bus

First level package design considerations for the IBM's S/390 G5 server

Bus pumping at Gbits/s rate on MCM

Determination of the optimal signal/ground configuration of a multi-pins connector for minimal crosstalk

Design methodology for on-chip interconnects

Signal propagation on seamless high off-chip connectivity (SHOCC) interconnects

Frequency-dependent crosstalk modeling for on-chip interconnections

Flip-chip power distribution

National Institute of Standards and Technology programs in electrical measurements for electronic interconnections

Inductance measurement of lead-frame packages

High frequency limitations of the JEDEC 123 guideline

Electrical characterization of ball grid array packages from S-parameter measurements below 500 MHz

On-chip capacitor measurement for high performance microprocessor

Characterization of frequency dependent dielectric packaging media using differential and multiple-reflection techniques on a precision stripline test structure

PLL phase error and power supply noise [microprocessors]

A novel high isolation interconnect for broadband mixed signal silicon MMICs

Investigations of multi-layer ceramic-based MCM technology

Modeling of free space holographic optical link for board level interconnect

Temperature stable thermoplastic microwave materials and copper laminates

Considerations of characterizing standard SMT packages for RFIC applications

A novel electrical performance analysis for leaded packages

Simulation and evaluation of ground bounce induced crosstalk in a mixed logic ball grid array substrate design

A custom package autoprober

GaAs multichip packaging using the selectively oxidized porous silicon (SOPS) substrate

Modeling of the electrical performance of the power and ground supply for a PC microprocessor on a card

Transient and crosstalk analysis of interconnection lines for single level integrated packaging modules

Scaling analysis of interconnectivity and crosstalk in VLSI circuits

Skin effects models for transmission line structures using generic SPICE circuit simulators

Evaluation and optimization of MCM-BGA packages

Full-wave electromagnetic modeling of interconnects with meshed ground planes

Fast method for the prediction of the capacitance of via through-holes

Electromagnetic interference through slots in packaging structures

Multi drop net topologies for MCM off chip interconnection lines

High frequency equivalent circuit model of via

Modeling of power distribution systems in PCs

Accurate power supply and ground plane pair models

Extraction of equivalent circuit models of package power supply distribution systems from full wave EM field simulations

Incorporating vertical discontinuities in power-bus modeling using a mixed-potential integral equation and circuit extraction formulation

Effects of power/ground via distribution on the power/ground performance of C4/BGA packages

Reducing simultaneous switching noise and EMI on ground/power planes by dissipative edge termination

Contribution of resonance to ground bounce in lossy thin film planes

Characterization of flip-chip CMOS ASIC simultaneous switching noise on multilayer organic and ceramic BGA/CGA packages

Norton equivalent model of microprocessor core noise from measurements

Rejection of SSN coupling in multilayer PCB using a conductive layer

Modeling and simulation of thin film decoupling capacitors

Power decoupling with integral capacitors and area array connections

ESR and ESL of ceramic capacitor applied to decoupling applications

Analytic modeling of monolithic inductors on semiconductor substrates

Simple formulas to calculate the line parameters of interconnects on conducting substrates

CAD-oriented equivalent circuit modeling of on-chip interconnects in CMOS technology

Microwave and millimeter wave ball grid array (BGA) packages

Electrical modeling of a BGA package for microwave applications-a layer by layer approach

Full wave analysis and development of circuit models for flip chip interconnects

Micromachined silicon conformal packaging for millimeter wave system applications

A monolithic spiral transmission-line balun

Novel microstrip-to-stripline transitions for leakage suppression in multilayer microwave circuits

The application of the TLM method to the simulation of high-speed and high-complexity electronic systems

Numerical modeling of packaging effects using the finite-difference time-domain technique

Canonical package problem solved using six different codes

Improved integral formulations for fast 3-D method-of-moments solvers

Efficient computation of interconnect capacitances using the domain decomposition approach

Recent improvements for fast inductance extraction and simulation [packaging]

Model reduction for PEEC models including retardation

Passive model order reduction of multiconductor interconnects

Efficient simulation of high-speed distributed interconnects using Krylov-subspace techniques

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[1992 Proceedings] Electrical Performance of Electronic Packaging

Reaching the limits of CMOS technology

Content Provider	IEEE Xplore Digital Library
Author	Isaac, R.D.
Copyright Year	1998
Description	Author affiliation: IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA (Isaac, R.D.)
Abstract	Summary form only given. The remarkable characteristic of transistors that fuels the rapid growth of the information technology industry is that their speed increases and their production cost decreases as their size is reduced. No other product in manufacturing has this characteristic over the vast range of size reduction demonstrated by the transistor. Current transistors are 20 times faster and occupy less than 1% of the area of those built 20 years ago. It seems intuitively obvious that continued transistor area reduction by a factor of 2 every 3 years, as in Moore's Law, cannot be sustained forever. However, predictions of the size reduction limit or even of the pace of size reduction have proven to elude the most insightful scientists. The predicted limit has been dropping at nearly the same rate as transistor size. The current dominant transistor technology in large ICs, including microprocessors, is CMOS. By studying CMOS scaling, we conclude that IC performance increase will indeed lessen as transistor size is further reduced from what is currently achievable. The major technology elements considered in CMOS scaling projection are: (1) lithography to enable manufacture of devices with smaller dimensions, (2) transistor design for higher performance at smaller dimensions, (3) smaller wiring for on-chip interconnection, (4) stable circuits, (5) more productive design automation tools, (6) greater memory cell density, and (7) manageable capital costs. We review each of these elements and present our conclusions in this presentation.
File Size	92805
File Format	PDF
ISBN	0780349652
DOI	10.1109/EPEP.1998.733476
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-10-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Costs Fuels Information technology Manufacturing industries Production Moore's Law Microprocessors CMOS integrated circuits CMOS memory circuits
Content Type	Text
Resource Type	Article

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