NDLI: A power-performance scalable FPGA using configurable voltage domains and a design mapping tool

Content Provider	IEEE Xplore Digital Library
Author	Honore, F. Chandrakasan, A.
Copyright Year	2005
Description	Author affiliation: Microsystems Technol. Lab., Massachusetts Inst. of Technol., Cambridge, MA, USA (Honore, F.; Chandrakasan, A.)
Abstract	Power scaling in FPGA can be enabled with support for distributed configurable voltage domains and block-level control. Each configurable logic block (CLB) represents a unique power domain tile on the chip. Each tile can be configured independently to operate at high VDD, low VDD, or disabled. In this work, a customized design flow to support multiple on-chip voltage domains leverages existing commercial tools Astro and standard cell library enhanced with a few additional cells for power management. In this paper, the authors developed a power-aware place and route-tool to determine which non-critical paths can run at reduced voltage and to configure the various domains of the array accordingly. By introducing fine-grain hardware controls, power-aware FPGA forms the basis for a platform that allows for effective in-system energy delay tradeoffs for energy-constrained applications such as handheld wireless systems.
Starting Page	709
Ending Page	710
File Size	315680
Page Count	2
File Format	PDF
ISBN	0780393627
DOI	10.1109/FPL.2005.1515819
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-08-24
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Voltage Switches Routing Tiles Integrated circuit interconnections Logic Energy consumption Delay Circuit analysis
Content Type	Text
Resource Type	Article

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