NDLI: An efficient approach to hide the run-time reconfiguration from SW applications

Content Provider	IEEE Xplore Digital Library
Author	Yang Qu Soininen, J.-P. Nurmi, J.
Copyright Year	2005
Description	Author affiliation: VTT Electron., Oulu, Finland (Yang Qu; Soininen, J.-P.)
Abstract	Dynamically reconfigurable logic is becoming an important design unit in SoC system. A method to make the reconfiguration management transparent to software applications is required in order to make easier the design with such devices. In this paper, we present an efficient approach similar to the cache miss and the data replacement in modern computer system for the task. The main advantage is that the reconfiguration can be correctly issued without extra instructions inserted either manually by SW application programmers or automatically by compilers. The approach was validated in a real case design. In the Virtex2P20 implementation platform, the resource overhead was 2.45% in terms of the number of LUTs. Performance is measured in cycle-accurate simulation environment. The overhead is about equal when compared with an OS-based equivalent design that uses system calls and critical section code to manage the reconfiguration.
Starting Page	648
Ending Page	653
File Size	165881
Page Count	6
File Format	PDF
ISBN	0780393627
DOI	10.1109/FPL.2005.1515805
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-08-24
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Runtime Application software Programming profession Reconfigurable logic Acceleration Registers Embedded system Costs Coprocessors Program processors
Content Type	Text
Resource Type	Article

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