NDLI: Mapping an H.264/AVC decoder onto the ADRES reconfigurable architecture

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International Conference on Field Programmable Logic and Applications, 2005.

Proceedings. 2005 International Conference on Field Programmable Logic and Applications (IEEE Cat. No.05EX1155)

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Applying the small-world network to routing structure of FPGAs

MILP-based placement and routing for dataflow architecture

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An efficient and scalable architecture for neural networks with backpropagation learning

Automatic creation of domain-specific reconfigurable CPLDs for SOC

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Custom implementation of the coarse-grained reconfigurable ADRES architecture for multimedia purposes

Power and area optimization for multiple restricted multiplication

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Error modelling of dual fixed-point arithmetic and its application in field programmable logic

Real-time Handel-C based implementation of DV decoder

Address generation for FPGA RAMS for efficient implementation of real-time video processing systems

Novel FPGA-based implementation of median and weighted median filters for image processing

A dynamically reconfigurable Bluetooth Base Band Unit

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Measuring and utilizing the correlation between signal connectivity and signal positioning for FPGAs containing multi-bit building blocks

Timing aware interconnect prediction models for FPGAS

Multidimensional dynamic programming for homology search

Real-time generation of three-dimensional motion fields

Evaluation of ray casting on processor like reconfigurable architectures

A flexible circuit switched NOC for FPGA based systems

Energy efficient NoC for best effort communication

Fault tolerant XGFT network on chip for multi processor system on chip circuits

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FPGA-based implementation and comparison of recursive and iterative algorithms

Configurable hardware/software architecture for data acquisition implementation on FPGA

Defect tolerance in multiple-FPGA systems

Defect-tolerant FPGA switch block and connection block with fine-grain redundancy for yield enhancement

Heterogeneity exploration for multiple 2D filter designs

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A programmable logic architecture for prototyping clockless circuits

GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips

A Verilog RTL synthesis tool for heterogeneous FPGAs

Compilation and management of phase-optimized reconfigurable systems

Trident: an FPGA compiler framework for floating-point algorithms

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Generation and exploration of reconfigurable architectures using mathematical programming

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Communication synthesis in a multiprocessor environment

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On-chip communication topology synthesis for shared multi-bus based architecture

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Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysis

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An autonomous FPGA-based emulation system for fast fault tolerant evaluation

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Yield modelling and yield enhancement for FPGAs using fault tolerance schemes

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Hierarchical placement for large-scale FPAA

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Snort offloader: a reconfigurable hardware NIDS filter

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A run-time reconfigurable hardware infrastructure for IP-core evaluation and test

A high performance hardware architecture for an SAD reuse based hierarchical motion estimation algorithm for H.264 video coding

Statistical power estimation for FPGAs

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Efficient hardware architectures for modular multiplication on FPGAs

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FPGA implementation of an area-time efficient FIR filter core using a self-clocked approach

Optimization of start-up time and quiescent power consumption of FPGAs

QPF: efficient quadratic placement for FPGAs

Safe PLD-based programmable controllers

Performance and energy analysis of task-level graph transformation techniques for dynamically reconfigurable architectures

A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware

A framework for ODE-based multimodel biochemical simulations on an FPGAs

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Evaluation strategies for coarse grained reconfigurable architectures

FIGARO - an automatic tool flow for designs with dynamic reconfiguration

FPGA implementation of a GF(2/sup 2M/) multiplier for use in pairing based cryptosystems

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Integration of a NOC-based multimedia processing platform

LAMP: a tool suite for families of FPGA-based computational accelerators

Low power domain-specific reconfigurable array for discrete wavelet transforms targeting multimedia applications

Mapping an H.264/AVC decoder onto the ADRES reconfigurable architecture

Parameterized logic power consumption models for FPGA-based arithmetic

Performance improvements using coarse-grain reconfigurable logic in embedded SOCs

A configuration memory architecture for fast run-time reconfiguration of FPGAs

A novel toolset for the development of FPGA-like reconfigurable logic

A reconfigurable perfect-hashing scheme for packet inspection

An efficient approach to hide the run-time reconfiguration from SW applications

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An integrated framework for architecture level exploration of reconfigurable platform

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Finite field division implementation

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Netflow probe intended for high-speed networks

Performance tuning of iterative algorithms in signal processing

Run-time scheduling for random multi-tasking in reconfigurable coprocessors

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Efficient execution on reconfigurable devices using concepts of pipelining

Exploration of heterogeneous reconfigurable architectures

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FPGA implementation of an augmented reality application for visually impaired people

FPGA interconnect fault tolerance

Hardware emulation of a network on chip architecture based on a clockwork routed manhattan street network

Instruction set extension using Microblaze processor

Leveraging reconfigurability in the design process

Mechanoprocessor: modeling the rodent whisker sensory system using FPGA

Next generation architectures and CAD for power aware programmable fabrics

PAHLS: towards run-time synthesis for FPGAs

Reconfigurable architectures for real-time network anomaly detection

Requested-QOS driven runtime reconfiguration of mobile devices

Design of a dynamic reconfigurable multi-grained hardware architecture with adaptive runtime routing

Testing superscalar processors in functional mode

Mapping an H.264/AVC decoder onto the ADRES reconfigurable architecture

Content Provider	IEEE Xplore Digital Library
Author	Bingfeng Mei Veredas, F.-J. Masschelein, B.
Copyright Year	2005
Description	Author affiliation: IMEC, Leuven, Belgium (Bingfeng Mei)
Abstract	H.264/AVC video coding standard promises improved coding efficiency compared with other standards such as MPEG-2. However, its computational complexity is also increased significantly. Efficiently mapping H.264/AVC decoder onto a flexible platform presents a big challenge to existing architectures and design methodology. This paper describes the process and results of mapping H.264/AVC decoder onto the ADRES architecture (Mei et al., 2003), which is a flexible coarse-grained reconfigurable architecture template that tightly couples a VLIW processor and a coarse-grained array.
Starting Page	622
Ending Page	625
File Size	180166
Page Count	4
File Format	PDF
ISBN	0780393627
DOI	10.1109/FPL.2005.1515799
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-08-24
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic voltage control Decoding Reconfigurable architectures Computer architecture Filters Video coding Computational complexity VLIW Digital video broadcasting Entropy
Content Type	Text
Resource Type	Article

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