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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Smith, A.M. Constantinides, G.A. Cheung, P.K.K. |
| Copyright Year | 2005 |
| Description | Author affiliation: Dept. of Electr. & Electron. Eng., Imperial Coll. London, UK (Smith, A.M.; Constantinides, G.A.; Cheung, P.K.K.) |
| Abstract | The purpose of this paper is to detail a high-level analytical modelling and optimisation environment for mixed-granularity field programmable gate arrays (FPGAs). The work carried out for the purposes of this study involves the creation of an analytical framework that can be used to optimise the design of a reconfigurable device for a set of benchmarks. The strengths of this approach are the simultaneous placement, module selection and architecture generation. In this paper, the problem is cast as a formal optimisation, and may be solved using existing optimisation tools. In addition, the approach is adapted into an heuristic for larger benchmark sets. The design space is explored by examining the tradeoffs between area, speed and flexibility, and some comparisons to commercial architectures are drawn. |
| Starting Page | 341 |
| Ending Page | 346 |
| File Size | 214942 |
| Page Count | 6 |
| File Format | |
| ISBN | 0780393627 |
| DOI | 10.1109/FPL.2005.1515745 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2005-08-24 |
| Publisher Place | Finland |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Reconfigurable architectures Mathematical programming Field programmable gate arrays Computer architecture Table lookup Educational institutions Analytical models Design optimization Programmable logic arrays Throughput |
| Content Type | Text |
| Resource Type | Article |
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