NDLI: A programmable logic architecture for prototyping clockless circuits

Content Provider	IEEE Xplore Digital Library
Author	Fesquet, L. Renaudin, M.
Copyright Year	2005
Description	Author affiliation: TIMA Lab., Grenoble, France (Fesquet, L.; Renaudin, M.)
Abstract	This paper presents a novel programmable logic device (PLD) architecture for implementing and prototyping various styles of clockless or asynchronous circuits. Many classes of asynchronous circuits exist, depending on the timing assumptions that are made at the logical level and the adopted handshake communication protocols. The main objective of this work is to break the dependency between the PLD architecture dedicated to asynchronous logic and the logic style. Indeed, the PLDs dedicated to asynchronous logic are always style-oriented. The innovative aspects of this architecture are described in details. Moreover, the structure is well suited to be adapted with further asynchronous logic evolutions thanks to the architecture genericity. The programmable structure is flexible enough to be used with different logic styles and asynchronous design flows. As an example, a full-adder was implemented in two different styles of logic to demonstrate the PLD architecture flexibility. This work is included in a larger project called TAST, dedicated to the synthesis and the prototyping of multistyle logic asynchronous circuits.
Starting Page	293
Ending Page	298
File Size	547708
Page Count	6
File Format	PDF
ISBN	0780393627
DOI	10.1109/FPL.2005.1515737
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-08-24
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Programmable logic arrays Programmable logic devices Logic circuits Prototypes Clocks Asynchronous circuits Logic devices Timing Protocols Logic design
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Rapid prototyping asynchronous processor

An architecture for asynchronous FPGAs

A new configurable and scalable architecture for rapid prototyping of asynchronous designs for signal processing

Prototyping a 2.4 Gbit/s CRMA -II Dual-Ring ATM LAN and MAN

FPGA architecture for multi-style asynchronous logic [full-adder example]

New approaches to design asynchronous circuits on FPGAs

Hazard-free Muller Gates for Implementing Asynchronous Circuits on Xilinx FPGA

An FPGA for implementing asynchronous circuits

Architecture and CAD for FPGAs

A programmable logic architecture for prototyping clockless circuits

Similar Documents

Rapid prototyping asynchronous processor

An architecture for asynchronous FPGAs

A new configurable and scalable architecture for rapid prototyping of asynchronous designs for signal processing

Prototyping a 2.4 Gbit/s CRMA -II Dual-Ring ATM LAN and MAN

FPGA architecture for multi-style asynchronous logic [full-adder example]

New approaches to design asynchronous circuits on FPGAs

Hazard-free Muller Gates for Implementing Asynchronous Circuits on Xilinx FPGA

An FPGA for implementing asynchronous circuits

Architecture and CAD for FPGAs

A programmable logic architecture for prototyping clockless circuits