NDLI: Integration of a NOC-based multimedia processing platform

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International Conference on Field Programmable Logic and Applications, 2005.

Proceedings. 2005 International Conference on Field Programmable Logic and Applications (IEEE Cat. No.05EX1155)

CUSTARD - a customisable threaded FPGA soft processor and tools

A reconfigurable instruction memory hierarchy for embedded systems

Low-cost fully reconfigurable data-path for FPGA-based multimedia processor

FPGA PLB evaluation using quantified Boolean satisfiability

FELIX: using rewriting-logic for generating functionally equivalent implementations

Post-placement bdd-based decomposition for FPGAs

Hashing + memory = low cost, exact pattern matching

High-speed and memory efficient TCP stream scanning using FPGA

Mutable codesign for embedded protocol processing

Exploiting pipelining to tolerate wire delays in a programmable-reconfigurable processor

Applying the small-world network to routing structure of FPGAs

MILP-based placement and routing for dataflow architecture

Using DSP blocks for ROM replacement: a novel synthesis flow

An FPGA solver for WSAT algorithms

An efficient and scalable architecture for neural networks with backpropagation learning

Automatic creation of domain-specific reconfigurable CPLDs for SOC

An 11 GHz FPGA with test applications

Custom implementation of the coarse-grained reconfigurable ADRES architecture for multimedia purposes

Power and area optimization for multiple restricted multiplication

Programmable numerical function generators: architectures and synthesis method

Error modelling of dual fixed-point arithmetic and its application in field programmable logic

Real-time Handel-C based implementation of DV decoder

Address generation for FPGA RAMS for efficient implementation of real-time video processing systems

Novel FPGA-based implementation of median and weighted median filters for image processing

A dynamically reconfigurable Bluetooth Base Band Unit

DyNoC: A dynamic infrastructure for communication in dynamically reconfugurable devices

Measuring and utilizing the correlation between signal connectivity and signal positioning for FPGAs containing multi-bit building blocks

Timing aware interconnect prediction models for FPGAS

Multidimensional dynamic programming for homology search

Real-time generation of three-dimensional motion fields

Evaluation of ray casting on processor like reconfigurable architectures

A flexible circuit switched NOC for FPGA based systems

Energy efficient NoC for best effort communication

Fault tolerant XGFT network on chip for multi processor system on chip circuits

Modular partial reconfigurable in Virtex FPGAs

Configuration merging for adaptive computer applications

Context saving and restoring for multitasking in reconfigurable systems

An FPGA application with high speed serial transceiver running at sub nominal rate

FPGA-based implementation and comparison of recursive and iterative algorithms

Configurable hardware/software architecture for data acquisition implementation on FPGA

Defect tolerance in multiple-FPGA systems

Defect-tolerant FPGA switch block and connection block with fine-grain redundancy for yield enhancement

Heterogeneity exploration for multiple 2D filter designs

Highly automated FPGA synthesis of application-specific protocol processors

Ziggurat-based hardware Gaussian random number generator

Snow 2.0 IP core for trusted hardware

A novel asynchronous FPGA architecture design and its performance evaluation

A programmable logic architecture for prototyping clockless circuits

GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips

A Verilog RTL synthesis tool for heterogeneous FPGAs

Compilation and management of phase-optimized reconfigurable systems

Trident: an FPGA compiler framework for floating-point algorithms

FPGA-accelerated Bayesian learning for reconstruction of gene regulatory networks

Programmable and reconfigurable hardware architectures for the rapid prototyping of cellular automata

A hardware-in-the-loop system to evaluate the performance of small-world cellular automata

Generation and exploration of reconfigurable architectures using mathematical programming

An I/O mechanism on a dynamically reconfigurable processor - which should be moved: data or configuration?

Cluster architecture for reconfigurable signal processing engine for wireless communication

Communication synthesis in a multiprocessor environment

PGR: a software package for reconfigurable super-computing

On-chip communication topology synthesis for shared multi-bus based architecture

A parallel MPEG-4 encoder for FPGA based multiprocessor SoC

Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysis

Memory efficient design of an MPEG-4 video encoder for FPGAs

An autonomous FPGA-based emulation system for fast fault tolerant evaluation

On the reliability evaluation of SRAM-based FPGA designs

Yield modelling and yield enhancement for FPGAs using fault tolerance schemes

Fast FPGA placement using space-filling curve

Hierarchical placement for large-scale FPAA

Architecture-adaptive routability-driven placement for FPGAs

Generalizing square attack using side-channels of an AES implementation on an FPGA

Real-time feature extraction for high speed networks

Bitwise optimised CAM for network intrusion detection systems

High speed/low power architectures for the finite radon transform

Towards a reconfigurable tracking system

High performance stereo computation architecture

An emulation model for sequential ATPG-based bounded model checking

Accelerating molecular dynamics simulations with configurable circuits

A low-cost scalable pipelined reconfigurable architecture for simulation of digital circuits

An FPGA-based soft multiprocessor system for IPv4 packet forwarding

Snort offloader: a reconfigurable hardware NIDS filter

HAIL: a hardware-accelerated algorithm for language identification

A run-time reconfigurable hardware infrastructure for IP-core evaluation and test

A high performance hardware architecture for an SAD reuse based hierarchical motion estimation algorithm for H.264 video coding

Statistical power estimation for FPGAs

CPU-independent assembler in an FPGA

Design and test methodology for a reconfigurable PEM data acquisition electronics system

Dynamic reconfiguration with hardwired networks-on-chip on future FPGAs

Efficient embedded FPL resource usage for RNS-based polyphase DWT filter banks

Efficient FPGA implementation of Cordic algorithm for circular and linear coordinates

Efficient hardware architectures for modular multiplication on FPGAs

Energy management in battery-powered sensor networks with reconfigurable computing nodes

FPGA implementation of an area-time efficient FIR filter core using a self-clocked approach

Optimization of start-up time and quiescent power consumption of FPGAs

QPF: efficient quadratic placement for FPGAs

Safe PLD-based programmable controllers

Performance and energy analysis of task-level graph transformation techniques for dynamically reconfigurable architectures

A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware

A framework for ODE-based multimodel biochemical simulations on an FPGAs

Area-efficient 2D shift-variant convolvers for FPGA-based digital image processing

Design and FPGA implementation of an embedded real-time biologically plausible spiking neural network processor

Evaluation strategies for coarse grained reconfigurable architectures

FIGARO - an automatic tool flow for designs with dynamic reconfiguration

FPGA implementation of a GF(2/sup 2M/) multiplier for use in pairing based cryptosystems

FPGA's middleware for software defined radio applications

Implementation of ranking filters on general purpose and reconfigurable architecture based on high density FPGA devices

Integration of a NOC-based multimedia processing platform

LAMP: a tool suite for families of FPGA-based computational accelerators

Low power domain-specific reconfigurable array for discrete wavelet transforms targeting multimedia applications

Mapping an H.264/AVC decoder onto the ADRES reconfigurable architecture

Parameterized logic power consumption models for FPGA-based arithmetic

Performance improvements using coarse-grain reconfigurable logic in embedded SOCs

A configuration memory architecture for fast run-time reconfiguration of FPGAs

A novel toolset for the development of FPGA-like reconfigurable logic

A reconfigurable perfect-hashing scheme for packet inspection

An efficient approach to hide the run-time reconfiguration from SW applications

An FPGA network architecture for accelerating 3DES - CBC

An integrated framework for architecture level exploration of reconfigurable platform

Coping with uncertainty in FPGA architecture design

Efficient scheduling of rate law functions for ODE-based multimodel biochemical simulation on an FPGA

Finite field division implementation

FPGA-aware garbage collection in Java

High-throughput reconfigurable computing: design and implementation of an IDEA encryption cryptosystem on the SRC-6E reconfigurable computer

Magnetic remanent memory structures for dynamically reconfigurable FPGA

Mullet - a parallel multiplier generator

Netflow probe intended for high-speed networks

Performance tuning of iterative algorithms in signal processing

Run-time scheduling for random multi-tasking in reconfigurable coprocessors

A low-energy FPGA: architecture design and software-supported design flow

A power-performance scalable FPGA using configurable voltage domains and a design mapping tool

An approach to scalable molecular dynamics simulation using supercomputing adaptive processing elements

Computer arithmetic synthesis technologies on reconfigurable platforms

Dual fixed-point: an efficient alternative to floating-point computation for DSP applications

Efficient execution on reconfigurable devices using concepts of pipelining

Exploration of heterogeneous reconfigurable architectures

FPGA finite difference time domain solver for thermal simulation

FPGA implementation of an augmented reality application for visually impaired people

FPGA interconnect fault tolerance

Hardware emulation of a network on chip architecture based on a clockwork routed manhattan street network

Instruction set extension using Microblaze processor

Leveraging reconfigurability in the design process

Mechanoprocessor: modeling the rodent whisker sensory system using FPGA

Next generation architectures and CAD for power aware programmable fabrics

PAHLS: towards run-time synthesis for FPGAs

Reconfigurable architectures for real-time network anomaly detection

Requested-QOS driven runtime reconfiguration of mobile devices

Design of a dynamic reconfigurable multi-grained hardware architecture with adaptive runtime routing

Testing superscalar processors in functional mode

Integration of a NOC-based multimedia processing platform

Content Provider	IEEE Xplore Digital Library
Author	Ahonen, T. Nurmi, J.
Copyright Year	2005
Description	Author affiliation: Inst. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland (Ahonen, T.; Nurmi, J.)
Abstract	At Tampere University of Technology we are developing a multimedia processing platform using previously designed IP components. The utilized components include the Proteo network-on-chip, the coffee processor, the milk floating point coprocessor, and the transport triggered TACO for protocol processing. Unlike shared buses, networks-on-chip support varying levels of communication parallelism depending on the topology. This design case illustrates the need to match the network topology and the interfaces to the computation models. Characteristics of the platform prototype on FPGA are described together with our approach to enable efficient utilization of the communication resources through the bus-oriented standard interfaces used.
Starting Page	606
Ending Page	611
File Size	350658
Page Count	6
File Format	PDF
ISBN	0780393627
DOI	10.1109/FPL.2005.1515796
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-08-24
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Network topology Network-on-a-chip Dairy products Coprocessors Transport protocols Parallel processing Computer interfaces Computer networks Computational modeling Prototypes
Content Type	Text
Resource Type	Article

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