NDLI: A dynamically reconfigurable Bluetooth Base Band Unit

Content Provider	IEEE Xplore Digital Library
Author	Esquiagola, J. Ozari, G. Teruya, M. Strum, M. Chau, W.
Copyright Year	2005
Description	Author affiliation: Microelectron. Lab., Polythecnic Sch. of Sao Paulo Univ., Brazil (Esquiagola, J.; Ozari, G.; Teruya, M.; Strum, M.; Chau, W.)
Abstract	In this paper, we present two different implementations of a dynamically reconfigurable Bluetooth Baseband Unit (BB/spl I.bar/Unit) using Xilinx Virtex-II FPGAs. The design flow started from a non-RTL SystemC model that has been functionally verified against an untimed SystemC golden model developed at Synopsys. This model was progressively refined (using Synopsys tools) until a synthesizable RTL model was obtained. The Xilinx modular design methodology was used to derive the partial and total bitstreams. Two partitions of the BB/spl I.bar/Unit were tested: header-payload (P1) and RX-TX (P2). The best results were obtained for the P2 partition on a XC2V250 component. Such a partition requires three sequential time intervals to process a Bluetooth packet: t/spl I.bar/rec + 1/spl I.bar/ini + t/spl I.bar/proc. The reconfigurable area occupied 4 columns and 24 bus-macros requiring a reconfiguration time of t/spl I.bar/rec=480 /spl mu/s, much smaller than the time slot of 625 is specified to either transmit or receive a packet.
Starting Page	148
Ending Page	152
File Size	315415
Page Count	5
File Format	PDF
ISBN	0780393627
DOI	10.1109/FPL.2005.1515714
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-08-24
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Bluetooth Baseband Field programmable gate arrays Design methodology Hardware Communication standards Standards development Microelectronics Laboratories Testing
Content Type	Text
Resource Type	Article

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