NDLI: Compilation and management of phase-optimized reconfigurable systems

Content Provider	IEEE Xplore Digital Library
Author	Styles, H. Luk, W.
Copyright Year	2005
Description	Author affiliation: Dept. of Comput., Imperial Coll., London, UK (Styles, H.; Luk, W.)
Abstract	A program phase is an interval over which the working set of the program remains more or less constant. This paper presents a dynamic optimization scheme which uses program phase information to optimize designs for reconfigurable computing. We present a mathematical formulation of the optimization problem and propose a solution which comprises of: (1) a hardware compilation scheme for generating configurations that are specialized for different phases of execution. (2) A runtime system which manages interchange of these configurations to maintain specialization between phase transitions. We report experimental results for Xilinx Virtex FPGAs involving OpenGL SFHCview-perf benchmarks and demonstrate 95.39% speedup over an optimized uniform rate static design and 11.13% speedup over an optimized multiinitiation interval static design. We present a framework for a posteriori performance analysis and architectural exploration with which we (a) establish a performance upper bound under perfect phase optimization, (b) investigate sensitivity to reconfiguration time, and (c) examine the quality of the proposed algorithm for phase-detection. The optimization is shown to be surprisingly insensitive to increased reconfiguration time. Faster reconfiguration yields limited benefits and performance improvements are possible up to 1 second reconfiguration time.
Starting Page	311
Ending Page	316
File Size	265187
Page Count	6
File Format	PDF
ISBN	0780393627
DOI	10.1109/FPL.2005.1515740
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-08-24
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design optimization Runtime Field programmable gate arrays Microprocessors Costs Educational institutions Performance analysis Phase detection Roads Predictive models
Content Type	Text
Resource Type	Article

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