NDLI: On-chip communication topology synthesis for shared multi-bus based architecture

Content Provider	IEEE Xplore Digital Library
Author	Sujan Pandey Glesner, M. Muhlhauser, M.
Copyright Year	2005
Description	Author affiliation: Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany (Sujan Pandey; Glesner, M.)
Abstract	This paper presents a method of on-chip commaunication topology synthesis for a shared multi-bus based architecture. An assumption for the synthesis is that the system has already been partitioned and mapped onto the appropriate components of a SoC so that size of data to be transferred at each time by an on-chip module is fixed. We model the communication behavior of each module as a set of communication lifetime intervals (CLTIs), which are optimized in terms of number of overlaps among them, size of bus width and the minimum number of buses, using ILP (integer linear programming) formulation. These optimized CLTIs are later given to the communication topology synthesis algorithm, which gives the number of buses and their interconnection. The results of applying this approach to the Talking Assistant used in ubiquitous computing application demonstrate the utility of our techniques to synthesize a custom on-chip shared multibus based communication architecture for a complex system.
Starting Page	374
Ending Page	379
File Size	232556
Page Count	6
File Format	PDF
ISBN	0780393627
DOI	10.1109/FPL.2005.1515750
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-08-24
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Topology System-on-a-chip Integer linear programming Ubiquitous computing Mobile communication Microelectronics Computer architecture Electronics industry System performance Costs
Content Type	Text
Resource Type	Article

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