NDLI: GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips

Content Provider	IEEE Xplore Digital Library
Author	Quartana, J. Renane, S. Baixas, A. Fesquet, L. Renaudin, M.
Copyright Year	2005
Description	Author affiliation: TIMA Lab., Grenoble, France (Quartana, J.; Renane, S.; Baixas, A.; Fesquet, L.; Renaudin, M.)
Abstract	This paper presents an innovating methodology for network-centric globally-asynchronous locally-synchronous (GALS) system prototyping. High-performance multiclock FPGAs are exploited for easy and fast prototyping of GALS systems based of an asynchronous network-on-chip (ANoC) interfacing synchronous standard IP cores. Modularity property of asynchronous circuits is fully exploited to design regular distributed interconnect topologies by the means of basic topology-free building blocks, with a focus and special design effort to solve arbitration and synchronization problems. A case-study is implemented on an up-to-date FPGA which includes two independently clocked processors, memory banks, serial and parallel communication links and an asynchronous DES (data encryption standard) module connected through an asynchronous 5/spl times/5 crossbar. The clock-less modules are implemented using a quasidelay insensitive logic on the FPGA by the means of a dedicated library. Performance figures are reported on the FPGA platform, especially for communication costs, speed and latency of the ANoC.
Starting Page	299
Ending Page	304
File Size	206916
Page Count	6
File Format	PDF
ISBN	0780393627
DOI	10.1109/FPL.2005.1515738
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-08-24
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Prototypes Field programmable gate arrays Network-on-a-chip Clocks Asynchronous circuits Integrated circuit interconnections Network topology Circuit topology Synchronization Cryptography
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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