NDLI: Efficient execution on reconfigurable devices using concepts of pipelining

Content Provider	IEEE Xplore Digital Library
Author	Dittmann, F.
Copyright Year	2005
Description	Author affiliation: Heinz Nixdorf Inst., Paderborn Univ., Germany (Dittmann, F.)
Abstract	The efficiency of algorithms on reconfigurable devices can be increased significantly using concepts of pipelining. However, pipelining must not necessarily be limited to introduce temporal parallelism to the execution paths on the reconfigurable device. It also can help to hide the often long reconfiguration time in the case of dynamic run time reconfiguration, i.e., during processing in one area, another one can be reconfigured. This work formulates the stages on run time reconfigurable systems and shows how to derive optimal partitioning of reconfiguration area with respect to the characteristics of the algorithms to be mapped and the characteristics of the execution platform. The goal of the thesis is to develop a comprehensive model for efficient execution of algorithms on run time reconfigurable systems referring to pipeline based run time reconfiguration.
Starting Page	717
Ending Page	718
File Size	1054463
Page Count	2
File Format	PDF
ISBN	0780393627
DOI	10.1109/FPL.2005.1515823
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-08-24
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipeline processing Hardware Partitioning algorithms Switches Parallel processing Displays Field programmable gate arrays Flow graphs Delay
Content Type	Text
Resource Type	Article

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