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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Fang Zhong Capson, D.W. Schuurman, D.C. |
| Copyright Year | 2008 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, ON (Fang Zhong; Capson, D.W.) |
| Abstract | This paper describes a parallel architecture for image feature detection implemented using an FPGA. The image features are detected using a localized PCA (principle component analysis) pattern matching scheme. An offline training phase identifies sub-windows surrounding salient points in an object which are then projected into eigenspace. Sub-windows from an input image can then be projected into the same eigenspace in order to recognize the same feature points in other images. An FPGA is developed to sequentially project a 10times10 sub-window surrounding each and every pixel into eigenspace so that features can be detected in an image. The FPGA uses parallel dot-product blocks with parallel multipliers and parallel comparators to enable rapid feature detection for sub-windows. Simulations are performed to determine the feasibility of using an FPGA along with the number of required logic elements and the timing requirements. |
| Starting Page | 001341 |
| Ending Page | 001344 |
| File Size | 180368 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424416424 |
| ISSN | 08407789 |
| DOI | 10.1109/CCECE.2008.4564758 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-05-04 |
| Publisher Place | Canada |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Parallel architectures Principal component analysis Computer vision Field programmable gate arrays Image analysis Pattern analysis Pattern matching Image recognition Pixel Logic FPGA PCA |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Hardware and Architecture |
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