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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ttofis, C. Theocharides, T. |
| Copyright Year | 2014 |
| Description | Author affiliation: Dept. of ECE, Univ. of Cyprus, Nicosia, Cyprus (Ttofis, C.; Theocharides, T.) |
| Abstract | Stereo matching is a vital task in several emerging embedded vision applications requiring high-quality depth computation and real-time frame-rate. Although several stereo matching dedicated-hardware systems have been proposed in recent years, only few of them focus on balancing accuracy and speed. This paper proposes a hardware-based stereo matching architecture that aims to provide high accuracy and concurrently high performance in embedded vision applications. The proposed architecture integrates a compact and efficient design of the recently proposed guided image filter; an edge-preserving filter that reduces the hardware complexity of the implemented stereo algorithm, while at the same time maintains high-quality results. A prototype of the architecture has been implemented on a Kintex-7 FPGA board, achieving 60 fps for 720p resolution images. Moreover, the proposed design delivers leading accuracy when compared to state-of-the-art hardware implementations. |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 1087253 |
| Page Count | 6 |
| File Format | |
| ISBN | 9783981537024 |
| DOI | 10.7873/DATE.2014.369 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-03-24 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | European Design Automation Association (EDAA) |
| Subject Keyword | Hardware Computer architecture Accuracy Matched filters Field programmable gate arrays Real-time systems Algorithm design and analysis FPGAs Stereo Matching Embedded Systems |
| Content Type | Text |
| Resource Type | Article |
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