NDLI: A tightly-coupled hardware controller to improve scalability and programmability of shared-memory heterogeneous clusters

Content Provider	IEEE Xplore Digital Library
Author	Burgio, P. Danilo, R. Marongiu, A. Coussy, P. Benini, L.
Copyright Year	2014
Description	Author affiliation: LabSTICC, Univ. de Bretagne-Sud, Lorient, France (Danilo, R.; Coussy, P.) \|\| DEI, Univ. degli Studi di Bologna, Bologna, Italy (Burgio, P.; Marongiu, A.; Benini, L.)
Abstract	Modern designs for embedded many-core systems increasingly include application-specific units to accelerate key computational kernels with orders-of-magnitude higher execution speed and energy efficiency compared to software counterparts. A promising architectural template is based on heterogeneous clusters, where simple RISC cores and specialized HW units (HWPU) communicate in a tightly-coupled manner via L1 shared memory. Efficiently integrating processors and a high number of HW Processing Units (HWPUs) in such an system poses two main challenges, namely, architectural scalability and programmability. In this paper we describe an optimized Data Pump (DP) which connects several accelerators to a restricted set of communication ports, and acts as a virtualization layer for programming, exposing FIFO queues to offload “HW tasks” to them through a set of lightweight APIs. In this work, we aim at optimizing both these mechanisms, for respectively reducing modules area and making programming sequence easier and lighter.
Starting Page	1
Ending Page	4
File Size	460725
Page Count	4
File Format	PDF
ISBN	9783981537024
DOI	10.7873/DATE.2014.038
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-03-24
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Ports (Computers) Programming Optimization System-on-chip Hardware Computer architecture Integrated circuit interconnections
Content Type	Text
Resource Type	Article

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