NDLI: Towards verifying determinism of SystemC designs

Content Provider	IEEE Xplore Digital Library
Author	Le, H.M. Drechsler, R.
Copyright Year	2014
Description	Author affiliation: Inst. of Comput. Sci., Univ. of Bremen, Bremen, Germany (Le, H.M.; Drechsler, R.)
Abstract	Ensuring the correctness of high-level SystemC designs is an important and challenging problem in today's Electronic System Level (ESL) methodology. Prevalently, a design is checked against a functional specification given by e.g. a testcase with reference output or a user-defined property. Another research direction takes the view of a SystemC design as a piece of concurrent software. The design is then checked for common concurrency problems and thus, a functional specification is not required. Along this line, several methods for deadlock detection and race analysis have been developed. In this work, we propose to consider a new concurrency verification problem, namely input-output determinism, for Sys-temC designs. That means for each possible input, the design must produce the same output under any valid process schedule. We argue that determinism verification is stronger than both deadlock detection and race analysis. Beside being an attractive correctness criterion itself, proven determinism helps to accelerate both simulative and formal verification. We also present a preliminary study to show the feasibility of determinism verification for SystemC designs.
Starting Page	1
Ending Page	4
File Size	172332
Page Count	4
File Format	PDF
ISBN	9783981537024
DOI	10.7873/DATE.2014.166
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-03-24
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Schedules Encoding System recovery Semantics Concurrent computing Delays Model checking
Content Type	Text
Resource Type	Article

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