NDLI: Extending lifetime of battery-powered coarse-grained reconfigurable computing platforms

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2015 Design, Automation & Test in Europe Conference & Exhibition (DATE)

2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Executive committee

Sponsors committee

Technical programme topic chairs

Technical programme committee

DATE Best Paper Awards [4 awards]

Call for papers

Table of contents

System design challenges for next generation wireless and embedded systems

The growing importance of microelectronics from a foundry perspective

Panel: Emerging vs. established technologies, a two sphinxes' riddle at the crossroads?

Emulation-based robustness assessment for automotive smart-power ICs

Startup error detection and containment to improve the robustness of hybrid FlexRay networks

A self-propagating wakeup mechanism for point-to-point networks with partial network support

Multi-variant-based design space exploration for automotive embedded systems

SAFE: Security-Aware FlexRay Scheduling Engine

Transient errors resiliency analysis technique for automotive safety critical applications

Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structures

Zonotope-based nonlinear model order reduction for fast performance bound analysis of analog circuits with multiple-interval-valued parameter variations

Implementation issues in the hierarchical composition of performance models of analog circuits

Modeling of an analog recording system design for ECoG and AP signals

Model based hierarchical optimization strategies for analog design automation

A novel low power 11-bit hybrid ADC using flash and delay line architectures

Semi-symbolic analysis of mixed-signal systems including discontinuities

Novel circuit topology synthesis method using circuit feature mining and symbolic comparison

An embedded offset and gain instrument for OpAmp IPs

Energy-efficient scheduling for memory-intensive GPGPU workloads

dSVM: Energy-efficient distributed Scratchpad Video Memory Architecture for the next-generation High Efficiency Video Coding

Feasibility exploration of NVM based I-cache through MSHR enhancements

EVX: Vector execution on low power EDGE cores

Program affinity performance models for performance and utilization

Advanced SIMD: Extending the reach of contemporary SIMD architectures

A tightly-coupled hardware controller to improve scalability and programmability of shared-memory heterogeneous clusters

On the correctness, optimality and precision of Static Probabilistic Timing Analysis

WCET-Centric dynamic instruction cache locking

Minimizing stack memory for hard real-time applications on multicore platforms

Time-predictable execution of multithreaded applications on multicore systems

Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales

Bias Temperature Instability analysis of FinFET based SRAM cells

SSFB: A highly-efficient and scalable simulation reduction technique for SRAM yield analysis

INFORMER: An integrated framework for early-stage memory robustness analysis

Wear-out analysis of Error Correction Techniques in Phase-Change Memory

Approximating the age of RF/analog circuits through re-characterization and statistical estimation

Technology transfer towards Horizon 2020

Panel: The world is going… analog & mixed-signal! What about EDA?

Lightweight code-based cryptography: QC-MDPC McEliece encryption on reconfigurable devices

On the assumption of mutual independence of jitter realizations in P-TRNG stochastic models

Clock-modulation based watermark for protection of embedded processors

Sensitivity-based weighting for passivity enforcement of linear macromodels in power integrity applications

Efficient analysis of variability impact on interconnect lines and resistor networks

Implicit index-aware model order reduction for RLC/RC networks

P/G TSV planning for IR-drop reduction in 3D-ICs

Package geometric aware thermal analysis by infrared-radiation thermal images

Cost-effective decap selection for beyond die power integrity

Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors

Mask-cost-aware ECO $routing^{∗}$

Coupling TDM NoC and DRAM controller for cost and performance optimization of real-time systems

Bus designs for time-probabilistic multicore processors

Programmable decoder and shadow threads: Tolerate remote code injection exploits with diversified redundancy

Exploiting narrow-width values for improving non-volatile cache lifetime

Partial-SET: Write speedup of PCM main memory

Attack-resilient sensor fusion

Bandwidth-efficient controller-server co-design with stability guarantees

Fault-tolerant control synthesis and verification of distributed embedded systems

Garbage collection for multi-version index on flash memory

D2Cyber: A design automation tool for dependable cybercars

Contract-based design of control protocols for safety-critical cyber-physical systems

Spatial pattern prediction based management of faulty data caches

Combined DVFS and mapping exploration for lifetime and soft-error susceptibility improvement in MPSoCs

DARP: Dynamically Adaptable Resilient Pipeline design in microprocessors

A fault detection mechanism in a Data-flow scheduled Multithreaded processor

Mission profile aware IC design — A case study

Mission profile aware robustness assessment of automotive power devices

Application of Mission Profiles to enable cross-domain constraint-driven design

Monitoring and WCET analysis in COTS multi-core-SoC-based mixed-criticality systems

Hardware virtualization support for shared resources in mixed-criticality multicore systems

ARO-PUF: An aging-resistant ring oscillator PUF design

An efficient reliable PUF-based cryptographic key generator in 65nm CMOS

Increasing the efficiency of syndrome coding for PUFs with helper data compression

Key-recovery attacks on various RO PUF constructions via helper data manipulation

IIR filters using stochastic arithmetic

Efficient transient thermal simulation of 3D ICs with liquid-cooling and through silicon vias

A logic integrated optimal pin-count design for digital microfluidic biochips

Fast and accurate computation using stochastic circuits

Achieving efficient packet-based memory system by exploiting correlation of memory requests

ALLARM: Optimizing sparse directories for thread-local data

Introducing Thread Criticality awareness in Prefetcher Aggressiveness Control

A multi banked — Multi ported — Non blocking shared L2 cache for MPSoC platforms

DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy

Reducing set-associative L1 data cache energy by early load data dependence detection $(ELD^{3})$

Distributed cooperative shared last-level caching in tiled multiprocessor system on chip

EATBit: Effective automated test for binary translation with high code coverage

On-device objective-C application optimization framework for high-performance mobile processors

Code generation for embedded heterogeneous architectures on android

Design of safety critical systems by refinement

Energy optimization in Android applications through wakelock placement

A wear-leveling-aware dynamic stack for PCM memory in embedded systems

Lifetime holes aware register allocation for clustered VLIW processors

Real-time trust evaluation in integrated circuits

Verification-guided voter minimization in triple-modular redundant circuits

Trade-offs in execution signature compression for reliable processor systems

An energy-aware fault tolerant scheduling framework for soft error resilient cloud computing systems

A low-power, high-performance approximate multiplier with configurable partial error recovery

Impact of resource sharing on performance and performance prediction

Time-critical computing on a single-chip massively parallel processor

Mapping mixed-criticality applications on multi-core architectures

Hacking and protecting IC hardware

Temporal memoization for energy-efficient timing error recovery in GPGPUs

Reliability-Aware Exceptions: Tolerating intermittent faults in microprocessor array structures

Temperature aware energy-reliability trade-offs for mapping of throughput-constrained applications on multimedia MPSoCs

Recovery-based resilient latency-insensitive systems

A Linux-governor based Dynamic Reliability Manager for android mobile devices

Yield and timing constrained spare TSV assignment for three-dimensional integrated circuits

Compiler-driven dynamic reliability management for on-chip systems under variabilities

Efficient high-sigma yield analysis for high dimensional problems

Sub-threshold logic circuit design using feedback equalization

Stochastic analysis of Bubble Razor

Minimizing state-of-health degradation in hybrid electrical energy storage systems with arbitrary source and load profiles

Dynamic Flip-Flop conversion to tolerate process variation in low power circuits

A low power and robust carbon nanotube 6T SRAM design with metallic tolerance

Scalable liveness verification for communication fabrics

Property directed invariant refinement for program verification

Simple interpolants for linear arithmetic

Tightening BDD-based approximate reachability with SAT-based clause $generalization^{∗}$

Make it real: Effective floating-point reasoning via exact arithmetic

RETLab: A fast design-automation framework for arbitrary RET networks

Design of 3D nanomagnetic logic circuits: A full-adder case study

Highly accurate SPICE-compatible modeling for single- and double-gate GNRFETs with studies on technology scaling

Rewiring for threshold logic circuit minimization

Width minimization in the Single-Electron Transistor array synthesis

Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints

Software-based Pauli tracking in fault-tolerant quantum circuits

Efficient SMT-based ATPG for interconnect open defects

Interconnect test for 3D stacked memory-on-logic

An effective approach to automatic functional processor test generation for small-delay faults

Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing

An efficient temperature-gradient based burn-in technique for 3D stacked ICs

Test and non-test cubes for diagnostic test generation based on merging of test cubes

New implementions of predictive alternate analog/RF test with augmented model redundancy

System integration — The bridge between More than Moore and More Moore

A landscape of the new dark silicon design regime

Integrated microfluidic power generation and cooling for bright silicon MPSoCs

Effective resource management towards efficient computing

Modeling steep slope devices: From circuits to architectures

Impact of steep-slope transistors on non-von Neumann architectures: CNN case study

Asynchronous design for new on-chip wide dynamic range power electronics

Real-time optimization of the battery banks lifetime in Hybrid Residential Electrical Systems

Optimal dimensioning of active cell balancing architectures

Optimal design and management of a smart residential PV and energy storage system

Design and fabrication of a 315 μΗ bondwire micro-transformer for ultra-low voltage energy harvesting

Providing regulation services and managing data center peak power budgets

The energy benefit of level-crossing sampling including the actuator's energy consumption

Design and evaluation of fine-grained power-gating for embedded microprocessors

SuperRange: Wide operational range power delivery design for both STV and NTV computing

Modeling and analysis of digital linear dropout regulators with adaptive control for high efficiency under wide dynamic range digital loads

Using MaxBMC for Pareto-optimal circuit initialization

Partial witnesses from preprocessed quantified Boolean formulas

Equivalence checking for function pipelining in behavioral synthesis

Towards the formal analysis of microresonators based photonic systems

SKETCHILOG: Sketching combinational circuits

Towards verifying determinism of SystemC designs

Library-based scalable refinement checking for contract-based design

Isochronous networks by construction

Tightly-coupled hardware support to dynamic parallelism acceleration in embedded shared memory clusters

p-OFTL: An object-based semantic-aware parallel flash translation layer

Using guided local search for adaptive resource reservation in large-scale embedded systems

Accelerating graph computation with racetrack memory and pointer-assisted graph representation

Nostradamus: Low-cost hardware-only error detection for processor cores

Word-line power supply selector for stability improvement of embedded SRAMs in high reliability applications

A high performance SEU-tolerant latch for nanoscale CMOS technology

A low-cost radiation hardened flip-flop

PSP-Cache: A low-cost fault-tolerant cache memory architecture

A hybrid non-volatile SRAM cell with concurrent SEU detection and correction

The connected car and its implication to the automotive chip roadmap

Cross layer resiliency in real world

Hardware/software approach for code synchronization in low-power multi-core sensor nodes

Hybrid memory architecture for voltage scaling in ultra-low power multi-core biomedical processors

Context aware power management for motion-sensing body area network nodes

A quality-scalable and energy-efficient approach for spectral analysis of heart rate variability

Battery aware stochastic QoS boosting in mobile computing devices

Exploiting expendable process-margins in DRAMs for run-time performance optimization

Cache aging reduction with improved performance using dynamically re-sizable cache

On GPU bus power reduction with 3D IC technologies

Process variation-aware workload partitioning algorithms for GPUs supporting spatial-multitasking

A thermal resilient integration of many-core microprocessors and main memory by 2.5D TSI I/Os

Leveraging on-chip networks for efficient prediction on multicore coherence

An adaptive Memory Interface Controller for improving bandwidth utilization of hybrid and reconfigurable systems

Asynchronous Asymmetrical Write Termination (AAWT) for a low power STT-MRAM

Write-once-memory-code phase change memory

Improving STT-MRAM density through multibit error correction

Energy efficient in-memory AES encryption based on nonvolatile domain-wall nanowire

ICE: Inline calibration for memristor crossbar-based computing engine

Complementary resistive switch based stateful logic operations using material implication

Scalability bottlenecks discovery in MPSoC platforms using data mining on simulation traces

Computing a language-based guarantee for timing properties of cyber-physical systems

Resource optimization for CSDF-modeled streaming applications with latency constraints

A layered approach for testing timing in the model-based implementation

Model-based protocol log generation for testing a telecommunication test harness using CLP

Time-decoupled parallel SystemC simulation

A unified methodology for a fast benchmarking of parallel architecture

Bit-Flipping Scan — A unified architecture for fault tolerance and offline test

Testing PUF-based secure key storage circuits

Making it harder to unlock an LSIB: Honeytraps and misdirection in a P1687 network

Co-optimization of memory BIST grouping, test scheduling, and logic placement

Power modeling and analysis in early design phases

System-level design methodology enabling fast development of baseband MP-SoC for 4G small cell base station

Virtual prototype life cycle in automotive applications

Extreme-scale computer architecture: Energy efficiency from the ground $up^{‡}$

Voltage island management in near threshold manycore architectures to mitigate dark silicon

Resolving the memory bottleneck for single supply near-threshold computing

Efficiency of a glitch detector against electromagnetic fault injection

Analyzing and eliminating the causes of fault sensitivity analysis

A smaller and faster variant of RSM

A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks

Energy efficient MIMO processing: A case study of opportunistic run-time approximations

Energy-efficient FPGA implementation for binomial option pricing using OpenCL

Hardware implementation of a Reed-Solomon soft decoder based on information set decoding

Ambient variation-tolerant and inter components aware thermal management for mobile system on chips

Energy efficient data flow transformation for Givens Rotation based QR Decomposition

Mode-Controlled Dataflow based modeling & analysis of a 4G-LTE receiver

An activity-sensitive contention delay model for highly efficient deterministic full-system simulations

Automatic specification granularity tuning for design space exploration

EDT: A specification notation for reactive systems

Model-based actor multiplexing with application to complex communication protocols

A novel model for system-level decision making with combined ASP and SMT solving

DeSpErate: Speeding-up design space exploration by using predictive simulation scheduling

Software architecture of High Efficiency Video Coding for many-core systems with power-efficient workload balancing

GPU-EvR: Run-time event based real-time scheduling framework on GPGPU platform

Multi-objective distributed run-time resource management for many-cores

CoMik: A predictable and cycle-accurately composable real-time microkernel

Utilization-aware load balancing for the energy efficient operation of the big.LITTLE processor

hevcDTM: Application-driven Dynamic Thermal Management for High Efficiency Video Coding

Improving efficiency of extensible processors by using approximate custom instructions

Efficient performance estimation with very small sample size via physical subspace projection and maximum a posteriori estimation

Joint Virtual Probe: Joint exploration of multiple test items' spatial patterns for efficient silicon characterization and test prediction

Substituting transition faults with path delay faults as a basic delay fault model

Standard cell library tuning for variability tolerant designs

Probabilistic standard cell modeling considering non-Gaussian parameters and correlations

Ultra-low power electronics with Si/Ge tunnel FET

Brain-inspired computing with spin torque devices

Toward ultralow-power computing at exteme with silicon carbide (SiC) nanoelectromechanical logic

III-V semiconductor nanowires for future devices

Advanced system on a chip design based on controllable-polarity FETs

Reconfigurable silicon nanowire devices and circuits: Opportunities and challenges

Advancing CMOS with carbon electronics

Application mapping for express channel-based networks-on-chip

Parallel probe based dynamic connection setup in TDM NoCs

ElastiStore: An elastic buffer architecture for Network-on-Chip routers

Dynamic construction of circuits for reactive traffic in homogeneous CMPs

Improving hamiltonian-based routing methods for on-chip networks: A turn model approach

Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks

A minimalist approach to Remote Attestation

Multi resolution touch panel with built-in fingerprint sensing support

HEROIC: Homomorphically EncRypted One Instruction Computer

EDA tools trust evaluation through security property proofs

Fast STA prediction-based gate-level timing simulation

A cross-level verification methodology for digital IPs augmented with embedded timing monitors

Empowering study of delay bound tightness with simulated annealing

Analysis and evaluation of per-flow delay bound for multiplexing models

Connecting different worlds — Technology abstraction for reliability-aware design and Test

Rate-adaptive tasks: Model, analysis, and design issues

Acceptance and random generation of event sequences under real time calculus constraints

General and efficient Response Time Analysis for EDF scheduling

The schedulability region of two-level mixed-criticality systems based on EDF-VD

Facilitating timing debug by logic path correspondence

Statistical static timing analysis using a skew-normal canonical delay model

Leakage-power-aware clock period minimization

A deep learning methodology to proliferate golden signoff timing

Aging-aware standard cell library design

Pass-XNOR logic: A new logic style for P-N junction based graphene circuits

Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designs

Memcomputing: The cape of good hope: [Extended special session description]

MSim: A general cycle accurate simulation platform for memcomputing studies

Energy-efficient hardware acceleration through computing in the memory

Exploring the limits of phase change memories

Magnetic memories: From DRAM replacement to ultra low power logic chips

Resistive memories: Which applications?

Thinfilm printed ferro-electric memories and integrated products

An adaptive transmitting power technique for energy efficient mm-wave wireless NoCs

Performance evaluation of wireless NoCs in presence of irregular network routing strategies

Low-latency wireless 3D NoCs via randomized shortcut chips

Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip

Failure analysis of a network-on-chip for real-time mixed-critical systems

Global fan speed control considering non-ideal temperature measurements in enterprise servers

Unveiling Eurora — Thermal and power characterization of the most energy-efficient supercomputer in the world

Contention aware frequency scaling on CMPs with guaranteed quality of service

Concurrent placement, capacity provisioning, and request flow control for a distributed cloud infrastructure

COOLIP: Simple yet effective job allocation for distributed thermally-throttled processors

Energy optimization in 3D MPSoCs with Wide-I/O DRAM using temperature variation aware bank-wise refresh

Automatic detection of concurrency bugs through event ordering constraints

Hardware-based fast exploration of cache hierarchies in application specific MPSoCs

SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives

Efficient simulation and modelling of non-rectangular NoC topologies

Moving from co-simulation to simulation for effective smart systems design

May-happen-in-parallel analysis based on segment graphs for safe ESL models

Timing analysis of First-Come First-Served scheduled interval-timed Directed Acyclic Graphs

A dynamic computation method for fast and accurate performance evaluation of multi-core architectures

Cross-correlation of specification and RTL for soft IP analysis

Thermal-aware frequency scaling for adaptive workloads on heterogeneous MPSoCs

Partitioned mixed-criticality scheduling on multiprocessor platforms

Generation of communication schedules for multi-mode distributed real-time applications

Provably minimal energy using coordinated DVS and power gating

A tree arbiter cell for high speed resource sharing in asynchronous environments

An efficient manipulation package for Biconditional Binary Decision Diagrams

Synthesis algorithm of parallel index generation units

Automating data reuse in High-Level Synthesis

A universal symmetry detection algorithm

Optimization of design complexity in time-multiplexed constant multiplications

Hardware primitives for the synthesis of multithreaded elastic systems

Organic electronics — From lab to markets

Spintronics for low-power computing

Chameleon: Channel efficient Optical Network-on-Chip

Low-voltage organic transistors for flexible electronics

Brisk and limited-impact NoC routing reconfiguration

Thermal management of manycore systems with silicon-photonic networks

Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline

DCM: An IP for the autonomous control of optical and electrical reconfigurable NoCs

Minimally buffered single-cycle deflection router

The metamodeling approach to system level synthesis

Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling

Formal verification of taint-propagation security properties in a commercial SoC design

Early design stage thermal evaluation and mitigation: The locomotiv architectural case

Multi-disciplinary integrated design automation tool for automotive cyber-physical systems

Predictive parallel event-driven HDL simulation with a new powerful prediction strategy

ArChiVED: Architectural checking via event digests for high performance validation

Coverage evaluation of post-silicon validation tests with virtual prototypes

Effective post-silicon failure localization using dynamic program slicing

Design-for-debug routing for FIB probing

Functional test generation guided by steady-state probabilities of abstract design

Automated system testing using dynamic and resource restricted clients

Scenario-aware data placement and memory area allocation for Multi-Processor System-on-Chips with reconfigurable 3D-stacked SRAMs

Optimized buffer allocation in multicore platforms

Memory-constrained static rate-optimal scheduling of synchronous dataflow graphs via retiming

A constraint-based design space exploration framework for real-time applications on MPSoCs

Reliability-aware mapping optimization of multi-core systems with mixed-criticality

From Simulink to NoC-based MPSoC on FPGA

Minimal sparse observability of complex networks: Application to MPSoC sensor placement and run-time thermal estimation & tracking

mDTM: Multi-objective dynamic thermal management for on-chip systems

Thermal management of batteries using a hybrid supercapacitor architecture

Thermal analysis and model identification techniques for a logic + WIDEIO stacked DRAM test chip

Adaptive power allocation for many-core systems inspired from multiagent auction model

Unified, ultra compact, quadratic power proxies for multi-core processors

Exploiting STT-NV technology for reconfigurable, high performance, low power, and low temperature functional unit design

A power-efficient reconfigurable architecture using PCM configuration technology

Extending lifetime of battery-powered coarse-grained reconfigurable computing platforms

3D FPGA using high-density interconnect Monolithic Integration

Joint communication scheduling and interconnect synthesis for FPGA-based many-core systems

A novel embedded system for vision tracking

GPGPUs: How to combine high computational power with high reliability

Integrated circuits processing chemical information: Prospects and challenges

Interfacing to living cells

Video analytics using beyond CMOS devices

Energy efficient neural networks for big data analytics

Special session: How secure are PUFs really? On the reach and limits of recent PUF attacks

PUFs at a glance

PUF modeling attacks: An introduction and overview

Hybrid side-channel/machine-learning attacks on PUFs: A new threat?

Physical vulnerabilities of Physically Unclonable Functions

Protocol attacks on advanced PUF protocols and countermeasures

Quo vadis, PUF?: Trends and challenges of emerging physical-disorder based security

Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs

A flexible ASIP architecture for connected components labeling in embedded vision applications

Image progressive acquisition for hardware systems

High-quality real-time hardware stereo matching based on guided image filtering

Optimization of standard cell based detailed placement for 16 nm FinFET process

Signature indexing of design layouts for hotspot detection

Metal layer planning for silicon interposers with consideration of routability and manufacturing cost

Non-intrusive integration of advanced diagnosis features in automotive E/E-architectures

ABACUS: A technique for automated behavioral synthesis of approximate computing circuits

Automatic generation of custom SIMD instructions for Superword Level Parallelism

System-level scheduling of real-time streaming applications using a semi-partitioned approach

ASLAN: Synthesis of approximate sequential circuits

VRCon: Dynamic reconfiguration of voltage regulators in a multicore platform

Coarse-grained Bubble Razor to exploit the potential of two-phase transparent latch designs

FEPMA: Fine-grained event-driven power meter for android smartphones based on device driver layer event monitoring

An analog non-volatile neural network platform for prototyping RF BIST solutions

Built-in self-test and characterization of polar transmitter parameters in the loop-back mode

A flexible BIST strategy for SDR transmitters

Sigma-delta testability for pipeline A/D converters

Panel: Future SoC verification methodology: UVM evolution or revolution?

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Extending lifetime of battery-powered coarse-grained reconfigurable computing platforms

Content Provider	IEEE Xplore Digital Library
Author	Shouyi Yin Peng Ouyang Leibo Liu Shaojun Wei
Copyright Year	2014
Description	Author affiliation: Inst. of Microelectron., Tsinghua Univ., Beijing, China (Shouyi Yin; Peng Ouyang; Leibo Liu; Shaojun Wei)
Abstract	The coarse-grained reconfigurable architecture (CGRA) is a promising platform for mobile computing. In this paper, how to prolong the lifetime of battery-powered reconfigurable computing platform is addressed. Considering the nonlinear characteristics of battery, a multi-objective optimization model is built for extending the lifetime of battery. Based on this model, a joint task-mapping and battery-scheduling method is proposed. The experimental results show that the proposed method achieves 26.22% improvement of battery runtime on average comparing to the state-of-the-art methods.
Starting Page	1
Ending Page	6
File Size	608637
Page Count	6
File Format	PDF
ISBN	9783981537024
DOI	10.7873/DATE.2014.350
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-03-24
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Batteries Runtime Energy consumption Scheduling Cost function Arrays
Content Type	Text
Resource Type	Article

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