NDLI: Exploiting narrow-width values for improving non-volatile cache lifetime

Content Provider	IEEE Xplore Digital Library
Author	Guangshan Duan Shuai Wang
Copyright Year	2014
Description	Author affiliation: Dept. of Comput. Sci. & Technol., Nanjing Univ., Nanjing, China (Guangshan Duan; Shuai Wang)
Abstract	Due to the high cell density, low leakage power consumption, and less vulnerability to soft errors, non-volatile memory technologies are among the most promising alternatives for replacing the traditional DRAM and SRAM technologies used in implementing main memory and caches in the modern microprocessor. However, one of the difficulties is the limited write endurance of most non-volatile memory technologies. In this paper, we propose to exploit the narrow-width values to improve the lifetime of non-volatile last level caches. Leading zeros masking scheme is first proposed to reduce the write stress to the upper half of the narrow-width data. To balance the write variations between the upper half and the lower half of the narrow-width data, two swap schemes, the swap on write (SW) and swap on replacement (SRepl), are proposed. To further reduce the write stress to non-volatile caches, we adopt two optimization schemes, the multiple dirty bit (MDB) and read before write (RBW), to improve their lifetime. Our experimental results show that by combining all our proposed schemes, the lifetime of non-volatile caches can be improved by 245% on average.
Starting Page	1
Ending Page	4
File Size	153305
Page Count	4
File Format	PDF
ISBN	9783981537024
DOI	10.7873/DATE.2014.065
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-03-24
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Nonvolatile memory Random access memory System-on-chip Stress Optimization Computer architecture Microprocessors
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Exploiting narrow-width values for improving non-volatile cache lifetime.

Exploiting narrow-width values for process variationtolerant 3-D microprocessors

$i^{2}WAP:$ Improving non-volatile cache lifetime by reducing inter- and intra-set write variations

Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors

Non-Volatile semiconductor memories for nano-scale technology

Emerging non-volatile memories: Opportunities and challenges

Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memory

A pure logic CMOS based low power non-volatile random access memory

Low-power hybrid STT/CMOS system-on-chip embedding non-volatile magnetic memory blocks

Exploiting narrow-width values for improving non-volatile cache lifetime

Similar Documents

Exploiting narrow-width values for improving non-volatile cache lifetime.

Exploiting narrow-width values for process variationtolerant 3-D microprocessors

$i^{2}WAP:$ Improving non-volatile cache lifetime by reducing inter- and intra-set write variations

Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors

Non-Volatile semiconductor memories for nano-scale technology

Emerging non-volatile memories: Opportunities and challenges

Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memory

A pure logic CMOS based low power non-volatile random access memory

Low-power hybrid STT/CMOS system-on-chip embedding non-volatile magnetic memory blocks

Exploiting narrow-width values for improving non-volatile cache lifetime