NDLI: Failure analysis of a network-on-chip for real-time mixed-critical systems

Content Provider	IEEE Xplore Digital Library
Author	Rambo, E.A. Tschiene, A. Diemer, J. Ahrendts, L. Ernst, R.
Copyright Year	2014
Description	Author affiliation: Inst. of Comput. & Network Eng., Tech. Univ. Braunschweig, Braunschweig, Germany (Rambo, E.A.; Tschiene, A.; Diemer, J.; Ahrendts, L.; Ernst, R.)
Abstract	Multi- and many-core architectures using Networks-on-Chip (NoC) are being explored for use in real-time safety-critical applications for their performance and efficiency. Such systems must provide isolation between tasks that may present distinct criticality levels. The NoC is critical to maintain the isolation property as it is a heavily used shared resource. To meet safety-standard requirements, such architectures require a systematic evaluation of the effects of all possible failures such as in the form of a Failure Mode and Effects Analysis (FMEA). We present the results of a detailed system-level analysis of a typical real-time mixed-critical network-on-chip architecture. This comprises an FMEA and error effects classification regarding duration and isolation violation.
Starting Page	1
Ending Page	4
File Size	180378
Page Count	4
File Format	PDF
ISBN	9783981537024
DOI	10.7873/DATE.2014.288
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-03-24
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Switches Ports (Computers) Fault tolerance Fault tolerant systems Real-time systems Computer architecture Routing
Content Type	Text
Resource Type	Article

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