NDLI: dSVM: Energy-efficient distributed Scratchpad Video Memory Architecture for the next-generation High Efficiency Video Coding

Content Provider	IEEE Xplore Digital Library
Author	Sampaio, F. Shafique, M. Zatt, B. Bampi, S. Henkel, J.
Copyright Year	2014
Description	Author affiliation: GACI, Fed. Univ. of Pelotas (UFPel), Pelotas, Brazil (Zatt, B.) \|\| Inf. Inst., Fed. Univ. of Rio Grande do Sul (UFRGS), Rio Grande, Brazil (Sampaio, F.; Bampi, S.) \|\| Dept. for Embedded Syst. (CES), Karlsruhe Inst. of Technol. (KIT), Karlsruhe, Germany (Shafique, M.; Henkel, J.)
Abstract	An energy-efficient distributed Scratchpad Video Memory Architecture (dSVM) for the next-generation parallel High Efficiency Video Coding is presented. Our dSVM combines private and overlapping (shared) Scratchpad Memories (SPMs) to support data reuse within and across different cores concurrently executing multiple parallel HEVC threads. We developed a statistical method to size and design the organization of the SPMs along with a supporting memory reading policy for energy efficiency. The key is to leverage the HEVC and video content knowledge. Furthermore, we integrate an adaptive power management policy for SPMs to manage the power states of different memory parts at run time depending upon the varying video content properties. Our experimental results illustrate that our dSVM architecture reduces the overall memory energy consumption by up to 51%-61% compared to parallelized state-of-the-art solutions [11]. The dSVM external memory energy savings increase with an increasing number of parallel HEVC threads and size of search window. Moreover, our SPM power management reacts to the current video properties and achieves up to 54% on-chip leakage energy savings.
Starting Page	1
Ending Page	6
File Size	543815
Page Count	6
File Format	PDF
ISBN	9783981537024
DOI	10.7873/DATE.2014.033
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-03-24
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Tiles Memory management Encoding System-on-chip Multicore processing Energy efficiency Video coding Adaptivity Video Memory Scratchpad Memory HEVC Application-Specific Optimizations Energy Efficiency
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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