NDLI: Low-power hybrid STT/CMOS system-on-chip embedding non-volatile magnetic memory blocks

Content Provider	IEEE Xplore Digital Library
Author	Layer, C. Jabeur, K. Gros, S. Becker, L. Paoli, P. Bernard-Granger, F. Javerliac, V. Dieny, B.
Copyright Year	2015
Description	Author affiliation: Univ. Grenoble Alpes, Grenoble, France (Layer, C.; Jabeur, K.; Gros, S.; Becker, L.; Paoli, P.; Bernard-Granger, F.; Javerliac, V.; Dieny, B.)
Abstract	Energy efficient computing has become the key to enable the portability of new applications onto mobile devices which need to be always smaller and more powerful. As the technology node shrinks, the leakage current increases exponentially in deep submicron CMOS, so that new strategies are required in integrated systems to save power without limiting processing performances. One of the solutions is to rely on NonVolatile Memories (NVM) and their integration within complex computing systems, but the association of heterogeneous technologies remains a real challenge. In this paper, we describe a fully embedded System-on-Chip (SoC), i.e., without external memory interface. We discuss the benefits of embedding NVM elements into the system in terms of power consumption and functionality enhancements compared to an equivalent system relying on standard volatile memory blocks. We depict the complete design from the block-diagram down to the layout of the fully functional non-volatile SoC. Our methodology includes the conception of a single bit memory cell up to the benchmarking of the architecture, in a hybrid magnetic/CMOS low-power technology, regarding the industrial constraints past experimentation in the aim to reach the quality of commercial products. We present precise pre-silicon performance estimations, using different configurations of compression algorithms as reference benchmarks that show where energy is mainly consumed.
Starting Page	1
Ending Page	4
File Size	412271
Page Count	4
File Format	PDF
ISBN	9781479988938
DOI	10.1109/NEWCAS.2015.7181999
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-07
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory System-on-chip Computer architecture Magnetic tunneling CMOS integrated circuits Integrated circuit modeling Nonvolatile memory
Content Type	Text
Resource Type	Article

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