NDLI: Content-driven memory pressure balancing and video memory power management for parallel high efficiency video coding

Please wait, while we are loading the content...

Low power design techniques in mobile processes

EcoLaser: an adaptive laser control for energy-efficient on-chip photonic interconnects

AxNN: energy-efficient neuromorphic systems using approximate computing

An on-chip autonomous thermoelectric energy management system for energy-efficient active cooling

Making $B^{+}-tree$ efficient in PCM-based main memory

Quasi-resonant clocking: a run-time control approach for true voltage-frequency-scalability

Dynamic thermal management for FinFET-based circuits exploiting the temperature effect inversion phenomenon

Challenges in low-power analog circuit design for sub-28nm CMOS technologies

Failing to fail: achieving success in advanced low power design using UPF

Accelerator-rich architectures: from single-chip to datacenters

GPUVolt: modeling and characterizing voltage noise in GPU architectures

Algorithms for power-efficient QoS in application specific NoCs

CASA: correlation-aware speculative adders

A case for leveraging 802.11p for direct phone-to-phone communications

2.3 ppm/°c 40 nW MOSFET-only voltage reference

Aging mitigation of power supply-connected batteries

QPR.js: a runtime framework for QoS-aware power optimization for parallel JavaScript programs

The new (system) balance of power and opportunities for optimizations

eDRAM-based tiered-reliability memory with applications to low-power frame buffers

Fast photovoltaic array reconfiguration for partial solar powered vehicles

A model for array-based approximate arithmetic computing with application to multiplier and squarer design

TONE: adaptive temperature optimization for the next generation video encoders

Tunnel FET-based ultra-low power, low-noise amplifier design for bio-signal acquisition

Sleep-aware variable partitioning for energy-efficient hybrid PRAM and DRAM main memory

An energy-efficient 2.5D through-silicon interposer I/O with self-adaptive adjustment of output-voltage swing

Buffered clock tree synthesis considering self-heating effects

Process and design solutions for exploiting FD-SOI technology towards energy efficient SOCs

Empirically derived abstractions in uncore power modeling for a server-class processor chip

Design and CAD methodologies for low power gate-level monolithic 3D ICs

Synergistic circuit and system design for energy-efficient and robust domain wall caches

Leakage mitigation techniques in smartphone SoCs

A bipolar ±40 mV self-starting boost converter with transformer reuse for thermoelectric energy harvesting

Variation tolerant design of a vector processor for recognition, mining and synthesis

Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell

Enabling high-performance LPDDRx-compatible MRAM

Energy harvesting from anti-corrosion power sources

SPINDLE: SPINtronic deep learning engine for large-scale neuromorphic computing

StoRM: a stochastic recognition and mining processor

Performance modeling for emerging interconnect technologies in CMOS and beyond-CMOS circuits

DR. Swap: energy-efficient paging for smartphones

Reconfigurable regenerator-based interconnect design for ultra-dynamic-voltage-scaling systems

Therminator: a thermal simulator for smartphones producing accurate chip and skin temperature maps

Unified embedded non-volatile memory for emerging mobile markets

Content-driven memory pressure balancing and video memory power management for parallel high efficiency video coding

Efficient NBTI modeling technique considering recovery effects

Timing errors in LDPC decoding computations with overscaled supply voltage

Impact of process variation in inductive integrated voltage regulator on delay and power of digital circuits

Thermal-aware layout planning for heterogeneous datacenters

a-SAD: power efficient SAD calculator for real time H.264 video encoder using MSB-approximation technique

SBAC: a statistics based cache bypassing method for asymmetric-access caches

Intelligent frame refresh for energy-aware display subsystems in mobile devices

Adaptive front-end throttling for superscalar processors

Approximate compressed sensing: ultra-low power biosignal processing via aggressive voltage scaling on a hybrid memory multi-core processor

Software canaries: software-based path delay fault testing for variation-aware energy-efficient design

Bridging high performance and low power in processor design

Design exploration of racetrack lower-level caches

Tag check elision

Powering the internet of things

A compact macromodel for the charge phase of a battery with typical charging protocol

Energy efficient task scheduling on a multi-core platform using real-time energy measurements

Energy-efficient mapping of biomedical applications on domain-specific accelerator under process variation

A memory rename table to reduce energy and improve performance

A deterministic-dither-based, all-digital system for on-chippower supply noise measurement

An open-source framework for formal specification and simulation of electrical energy systems

Analysis and optimization of in-situ error detection techniques in ultra-low-voltage pipeline

Quantifying the impact of variability on the energy efficiency for a next-generation ultra-green supercomputer

MIN: a power efficient mechanism to mitigate the impact of process variations on nanophotonic networks

EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors

A digital dynamic write margin sensor for low power read/write operations in 28nm SRAM

Smart butterfly: reducing static power dissipation of network-on-chip with core-state-awareness

Energy-efficient dot product computation using a switched analog circuit architecture

Gated low-power clock tree synthesis for 3D-ICs

Unlocking the true potential of 3D CPUs with micro-fluidic cooling

Prolonging PCM lifetime through energy-efficient, segment-aware, and wear-resistant page allocation

Content-driven memory pressure balancing and video memory power management for parallel high efficiency video coding

Content Provider	ACM Digital Library
Author	Henkel, Jörg Bampi, Sergio Shafique, Muhammad Sampaio, Felipe Martin Zatt, Bruno
Abstract	We present a novel content-driven memory pressure balancing and video memory power management scheme for parallel High Efficiency Video Coding (HEVC). The key is to leverage the application-specific knowledge to balance the (instant) access pressure on Scratchpad-based Video Memories (SVMs) for parallelized video processing. Our scheme accurately predicts the memory requirements of each processing core based on monitored memory usage and leverages this knowledge to perform a categorization of different video regions. Afterwards, it employs an adaptive policy for memory pressure balancing by rescheduling encoding of different video blocks based on their categories. This balancing also facilitates our scheme to perform efficient power-gating of unused parts of SVMs. Experimental results show that our scheme reduces the variations in the memory pressure by 37%-83% when compared to the traditional raster scan processing for 4- and 16-core parallelized HEVC encoder. Our content-driven power management saves 56% (on average) of SVM leakage energy.
Starting Page	153
Ending Page	158
Page Count	6
File Format	PDF
ISBN	9781450329750
DOI	10.1145/2627369.2627615
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-08-11
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Adaptivity Application-specific optimization Energy Memory pressure reduction Power management On-chip memory Hevc video coding Low-power
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in