NDLI: A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13μm CMOS technology

Content Provider	IEEE Xplore Digital Library
Author	Yu-Hao Hsu Ming-Hao Lu Ping-Lin Yang Fan-Ta Chen You-Hung Li Min-Sheng Kao Chih-Hsing Lin Ching-Te Chiu Jen-Ming Wu Shuo-Hung Hsu YarSun Hsu
Copyright Year	2008
Description	Author affiliation: Inst. of Commun. Eng., Nat. Tsing Hua Univ., Hsinchu (Yu-Hao Hsu; Ming-Hao Lu; Ping-Lin Yang; Fan-Ta Chen; You-Hung Li; Min-Sheng Kao; Chih-Hsing Lin; Ching-Te Chiu; Jen-Ming Wu; Shuo-Hung Hsu; YarSun Hsu)
Abstract	In this paper, we present a 7 Gbps/Ch quad SerDes integrated with a 4times4 load-balanced switch fabric circuit for high speed networking applications. To achieve high-speed and low area, we propose an area-saving RF model device for the SerDes design. The area-saving RF model has almost the same speed and jitter performance with the RF model but only consumes one half of the area. In our hybrid design of the SerDes architecture, the area-saving RF model mixed with the baseband model can reduce 75% of area compared with the design using only the conventional RF model. The grounded coplanar waveguide (GCPW) type transmission line is also employed to reduce the clock tree skew for the quad SerDes to within 1 ps. The total area is 3 mm times 2.48 mm, including the switch fabric, the quad SerDes interface, and a LC-PLL. In our results, each input/output port of the 4x4 switch fabric can achieve 7 Gbps data rate, and the overall throughout is 28 Gbps.
Starting Page	3086
Ending Page	3089
File Size	843749
Page Count	4
File Format	PDF
ISBN	9781424416837
DOI	10.1109/ISCAS.2008.4542110
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-05-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches CMOS technology Jitter Radio frequency Semiconductor device modeling Fabrics Integrated circuit technology Switching circuits High-speed networks Baseband
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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