NDLI: A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding

Content Provider	IEEE Xplore Digital Library
Author	Murachi, Y. Mizuno, K. Miyakoshi, J. Hamamoto, M. Iinuma, T. Ishihara, T. Fang Yin Jangchung Lee Kamino, T. Kawaguchi, H. Yoshimoto, M.
Copyright Year	2008
Description	Author affiliation: Dept. of Comput. Sci. & Syst. Eng., Kobe Univ., Kobe (Murachi, Y.; Mizuno, K.; Miyakoshi, J.; Hamamoto, M.; Iinuma, T.; Ishihara, T.; Fang Yin; Jangchung Lee; Kamino, T.; Kawaguchi, H.; Yoshimoto, M.)
Abstract	This paper describes a sub 100-mW H.264/AVC MP@L4.1 integer-pel motion estimation processor core for a low power video encoder. It supports macro block adaptive frame field (MBAFF) encoding and bi-directional prediction for a resolution of 1920times1080 pixels at 30 fps which haven't been realized by conventional methods. The proposed processor core features a novel hierarchical algorithm, a reconfigurable ring-connected systolic array architecture, and a segmentation- free rectangle-access search window buffer. The processor core has been designed in a 90 nm CMOS technology, and its core size is 2.5times2.5 $mm^{2}.$ With one core, one reference frame can be handled, and 48 mW is consumed at 1 V. Two-core configuration dissipates 96 mW for two reference frames.
Starting Page	848
Ending Page	851
File Size	406449
Page Count	4
File Format	PDF
ISBN	9781424416837
DOI	10.1109/ISCAS.2008.4541551
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-05-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic voltage control Motion estimation Very large scale integration Encoding Cyclic redundancy check Systolic arrays CMOS technology Search methods Computer architecture Image analysis
Content Type	Text
Resource Type	Article

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