NDLI: “Green” micro-architecture and circuit co-design for ternary content addressable memory

Content Provider	IEEE Xplore Digital Library
Author	Po-Tsang Huang Shu-Wei Chang Wen-Yen Liu Wei Hwang
Copyright Year	2008
Description	Author affiliation: Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu (Po-Tsang Huang; Shu-Wei Chang; Wen-Yen Liu; Wei Hwang)
Abstract	In this paper, an energy-efficient and high performance ternary content addressable memory (TCAM) are presented. It employs the concept of "green" microarchitecture and circuit co-design. For achieving energy-efficient TCAM architecture, hierarchy search-line scheme and butterfly match-line scheme are proposed. Moreover, the match-lines are also implemented by noise-tolerant XOR-based conditional keeper and don't-care based power gating scheme to reduce not only search time but power consumption. In order to reduce increasing leakage power with advanced technologies, furthermore, the proposed TCAM design employs super cut-off power gating technique and multi-mode data-retention power gating technique to reduce leakage currents without reducing search time and destroying noise margin. An energy-efficient 256times144 TCAM array is implemented in TSMC 0.13 um and designed in 65 nm Berkeley Predictive Technology Model, respectively. The simulation results show the leakage power reduction is 70.7% and energy metric of TCAM macro is 0.047 fJ/bit/search.
Starting Page	3322
Ending Page	3325
File Size	460614
Page Count	4
File Format	PDF
ISBN	9781424416837
DOI	10.1109/ISCAS.2008.4542169
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-05-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Associative memory Energy consumption Circuit noise Leakage current Computer aided manufacturing CADCAM Energy efficiency Noise reduction Cams Power engineering and energy
Content Type	Text
Resource Type	Article

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