NDLI: Binary de Bruijn interconnection network for a flexible LDPC/turbo decoder

Content Provider	IEEE Xplore Digital Library
Author	Moussa, H. Baghdadi, A. Jezequel, M.
Copyright Year	2008
Description	Author affiliation: Electron. Dept., Inst. TELECOM/TELECOM Bretagne, Brest (Moussa, H.; Baghdadi, A.; Jezequel, M.)
Abstract	This paper proposes a novel on-chip interconnection network adapted to a flexible multiprocessor LDPC/turbo decoder and based on the de Bruijn network. The main characteristics of this network -including its logarithmic diameter, scalable aggregate bandwidth, and optimized routing technique- allow it to efficiently support the communication- intensive nature of the two decoding techniques. We present a detailed hardware implementation of the routers and the network interfaces as well as the packet format and the routing algorithm. In order to evaluate the performance of the proposed network, a generic RTL VHDL description has been developed and synthesized with ST CMOS 0.18 mum technology. The flexibility and the scalability of this on-chip communication network enable it to be used in the emerging multi-code applications and standards. In addition, the results obtained for a 16-processor network demonstrate a major aggregate bandwidth of 296 Gbps with a relative small area of 3.56 $mm^{2}.$
Starting Page	97
Ending Page	100
File Size	269906
Page Count	4
File Format	PDF
ISBN	9781424416837
DOI	10.1109/ISCAS.2008.4541363
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-05-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiprocessor interconnection networks Parity check codes Decoding Network-on-a-chip Aggregates Bandwidth Routing CMOS technology Hardware Network interfaces
Content Type	Text
Resource Type	Article

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