NDLI: Binary translation process to optimize nanowire arrays usage

Content Provider	IEEE Xplore Digital Library
Author	Rhod, E.L. Rutzig, M.B. Carro, L.
Copyright Year	2008
Description	Author affiliation: Inst. de Inf., UFRGS, Porto Alegre (Rhod, E.L.; Rutzig, M.B.; Carro, L.)
Abstract	The last years of semiconductor research have allowed the construction of nanowires. These atomic structures promise to have more than one order of magnitude higher density when compared to 22 nm CMOS, with less power dissipation, but unfortunately with much lower switching speed. Although there are several works that deal with the problems related to specific fabrication issues, the best use of these structures from a design perspective is still an open field of research. The design solution should take into account available parallelism (to cope with these slower than CMOS devices) and reliability. Moreover, one has to tackle the software compatibility problem, in the sense that nanowire circuits are being considered as accelerators, and not a CMOS replacement. In this paper we propose the use of a nanowire array together with a binary translation mechanism that allows the coupling of the nanowire array to a regular microprocessor, and we show how can one expect high performance and low dissipation, while still considering the intrinsic reliability issue of nanowires.
Starting Page	396
Ending Page	399
File Size	367854
Page Count	4
File Format	PDF
ISBN	9781424416837
DOI	10.1109/ISCAS.2008.4541438
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-05-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Fabrication Wires CMOS technology Semiconductivity FETs Power dissipation Power semiconductor switches Coupling circuits Microprocessors
Content Type	Text
Resource Type	Article

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