NDLI: A current limiter for LDO regulators with internal compensation for process and temperature variations

Content Provider	IEEE Xplore Digital Library
Author	De Lima, J.A. Pimenta, W.A.
Copyright Year	2008
Description	Author affiliation: Brazil Semicond. Technol. Center, Campinas (De Lima, J.A.; Pimenta, W.A.)
Abstract	A current limiter that securely clamps the LDO output current upon load over-current is presented. Although the approach relies on absolute values of parameters such as resistance and MOSFET threshold voltage on subsequent I/V and V/I conversions of the LDO sensed current, a reference current to the arbitration circuit is derived in such a manner that the dependence of the clamping value $l_{CLP}$ on process and temperature variations is canceled out at good extent. Furthermore, the sense circuit uses a p-MOSFET depletion device to comply with very low dropouts. For a nominal value of 750 mA, minimum and maximum simulated values of $I_{CLP}$ are 570 mA and 930 mA, respectively, for a broad biases, process spread and temperatures ranging from -40degC to 150degC. An LDO with 400 mA-current capability and 250 mV-dropout embedding the proposed limiter was integrated on a high-voltage process. Experimental data attest the clamping functionality and accuracy of the proposed circuit for low and large dropouts.
Starting Page	2238
Ending Page	2241
File Size	227946
Page Count	4
File Format	PDF
ISBN	9781424416837
DOI	10.1109/ISCAS.2008.4541898
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-05-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Current limiters Regulators Temperature sensors Clamps Protection MOSFET circuits Threshold voltage Temperature dependence Circuit simulation Temperature distribution
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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