NDLI: Evolution of ESD process capability in future electronic industry

Content Provider	IEEE Xplore Digital Library
Author	Lin, Nakata Liang, Yun Wang, Paul Pelc, Tom
Copyright Year	2014
Description	Author affiliation: Quality Engineering, Oracle Corporation, California Redwood City, USA (Pelc, Tom) \|\| Global Quality and Manufacturer Technology Develop, MiTAC International, Inc, Shunde of Guangdong, China (Lin, Nakata; Liang, Yun; Wang, Paul)
Abstract	The evolution in semiconductor and electronic packaging to fulfill mobility and miniaturization has drastically changed the nature of electronic industry. Electronic component are continuing to get more sensitive to EOS (electrical overstress) due to electrostatic Sensitivity, Although HBM (Human Body Model) for Electrostatic sensitive device (ESD) has not changed for the last two decades. In this article, the CDM (Charged Device Model) which is used in semiconductor device ESD sensitivity test will be explained for a potential situation where a semiconductor device is charged to a high voltage then discharged to a grounded surface. From the failure analysis data collected from the field in the past several years, it is clear that the number of failure caused by ESD has been increasing due to component electrostatic as sensitivity as 100V of CDM. It is perilous to find out the possible ESD source and risk in PCBA/SYS assembly process and make the corresponding remedy before the electronic board is build in the line. This article will give the general guideline to make this extended ESD control, and a working model will be developed to organize the mitigation plan and measures to be taken.
Starting Page	1556
Ending Page	1560
File Size	812519
Page Count	5
File Format	PDF
ISBN	9781479938605
DOI	10.1109/ISAF.2014.6918160
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-05-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electrostatic discharges Connectors Electrical resistance measurement MOSFET Insulators Assembly Production ESD process control CDM Charged Device Model HBM Human Body Model
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Evolution of ESD process capability in future electronic industry

The failure mechanism re-investigation Of ESD device on EPI wafer

A hybrid ESD clamp with thyristor delay element and diodes for low-leakage applications

Skyworks capacitor model for ESD applications

Development of a New pHEMT-Based Electrostatic Discharge Protection Structure

Process ESD capability measurements

A low leakage poly-gated SCR device for ESD protection in 65nm CMOS process

A novel CDM-like discharge effect during human body model (HBM) ESD stress

Equipment ESD capability measurements

Evolution of ESD process capability in future electronic industry

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Evolution of ESD process capability in future electronic industry

The failure mechanism re-investigation Of ESD device on EPI wafer

A hybrid ESD clamp with thyristor delay element and diodes for low-leakage applications

Skyworks capacitor model for ESD applications

Development of a New pHEMT-Based Electrostatic Discharge Protection Structure

Process ESD capability measurements

A low leakage poly-gated SCR device for ESD protection in 65nm CMOS process

A novel CDM-like discharge effect during human body model (HBM) ESD stress

Equipment ESD capability measurements

Evolution of ESD process capability in future electronic industry