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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chen, F. Lloyd, J.R. Chanda, K. Achanta, R. Bravo, O. Strong, A. McLaughlin, P.S. Shinosky, M. Sankaran, S. Gebreselasie, E. Stamper, A.K. He, Z.X. |
| Copyright Year | 2008 |
| Description | Author affiliation: IBM Microelectron., Essex Junction, VT (Chen, F.) |
| Abstract | The study of low-k TDDB line space scaling is important for assuring robust reliability for new technologies. Although spacing effects due to line edge roughness (LER) on low-k TDDB lifetime were reported previously (Chen et al., 2007; Lloyd et al., 2007; Kim et al., 2007), there has been a lack of an analytical model with which to link line edge roughness to experimental TDDB data in a simple quantitative format. This work reports a thorough investigation into the low-k SiCOH line LER effect on low-k TDDB covering both experimental results and finite element modeling (FEM) simulations. The maximum electric field intensity as a result of sidewall LER bump was found to depend on the bump curvature. The decrease of low-k line spacing that resulted in a shorter TDDB lifetime even under the same applied electric field was then carefully analyzed. A simple analytical model of the effect of line edge roughness on TDDB failure time reduction is presented. This model was verified by experimental results. Additionally, a method to electrically quantify an overall line edge roughness is introduced. |
| Starting Page | 132 |
| Ending Page | 137 |
| File Size | 434799 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424420490 |
| DOI | 10.1109/RELPHY.2008.4558874 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-04-27 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Breakdown voltage Integrated circuit interconnections Stress Acceleration Analytical models Dielectric breakdown Dielectric materials Microelectronics Space technology Microscopy ILD time-dependent dielectric breakdown Cu interconnect line edge roughness reliability macroscopic line-to-line spacing variation microscopic line-to-line spacing variation spacing scaling low-k |
| Content Type | Text |
| Resource Type | Article |
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