NDLI: Memory design for high temperature radiation environments

Content Provider	IEEE Xplore Digital Library
Author	Tai-Hua Chen Clark, L.T. Holbert, K.E.
Copyright Year	2008
Description	Author affiliation: Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ (Tai-Hua Chen; Clark, L.T.; Holbert, K.E.)
Abstract	This paper presents bulk CMOS memory circuits capable of both ultra-low voltage (subthreshold, i.e., $V_{DD}$ less than the transistor threshold voltage $V_{th})$ low power operation and high temperature operation at nominal $V_{DD}.$ One of the memory designs is radiation hardened by design (RHBD) using interleaved DICE storage cells, enclosed transistor geometries, and P-type guard rings. The other is not hardened against radiation. Experimental results are presented showing that the room temperature minimum $V_{DD}$ of the hardened device remains essentially unchanged from the pre-irradiation $V_{DDMIN}$ = 210 mV value after Co-60 irradiation to 4 Mrad(Si). The standby power supply current $I_{SB}$ of the device increases less than 2x from this level of irradiation. The RHBD memory design has been tested to be operational at temperatures of 225degC. The combined effects of high temperature and irradiation are also investigated for both designs.
Starting Page	107
Ending Page	114
File Size	360074
Page Count	8
File Format	PDF
ISBN	9781424420490
DOI	10.1109/RELPHY.2008.4558870
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-04-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Photonic band gap Radiation hardening Temperature control Silicon on insulator technology Temperature distribution CMOS logic circuits CMOS memory circuits Threshold voltage Doping Monitoring
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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